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| 型号： | TSX68C000MCB/C12.5A |
| 厂商： | E2V TECHNOLOGIES PLC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 12.5 MHz, MICROPROCESSOR, CDIP64 |
| 封装： | CERAMIC, SDIP-64 |
| 文件页数： | 31/54页 |
| 文件大小： | 901K |
| 代理商： | TSX68C000MCB/C12.5A |
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37
0853B–HIREL–09/07
e2v semiconductors SAS 2007
TS68C000
Included in the register indirect addressing modes is the capability to do post incrementing, predecre-
menting, offsetting, and indexing. The program counter relative mode can also be modified via Indexing
and offsetting.
2.7.3
Data Transfer Operations
Transfer of data between devices involves the following leads:
1.
address bus A1 through A23,
2.
data bus 00 through D15, and
3.
control signals.
The address and data buses are separate parallel buses used to transfer data using an asynchronous
bus structure. In all cycles, the bus master assumes responsibility for deskewing all signals it issues at
bath the stan and end of a cycle. In addition, the bus master Is responsible for deskewing the acknowl-
edge and data signals tram the slave device.
The following paragraphs explain the read, write, and read-modify.write cycles. The indivisible read-
modify-write cycle is the method used by the TS68C000 for interlocked multiprocessor communications.
2.7.3.1
Read Cycle
During a read cycle, the processor receives data tram the memory of a peripheral devlce. The processor
reads bytes of data in all cases. If the instruction specifies a ward (or double ward) operation, the proces-
sor reads both upper and lower bytes simultaneously. by asserting both upper and lower data strobes.
When the instruction specifies byte operation, the processor uses an internal AO bit to determine which
byte to read and then Issues the data strobe required for that byte. For byte operations, when the AO bit
equals zero, the upper data strobes is issued. When the AO bit equals one, the lower data strobe is
issued. When the data is received, the processor correctly positions is internally.
2.7.3.2
Write Cycle
During a write cycle, the processor sends data to either the memory of a peripheral device. The proces-
sor writes bytes of data in all cases. If the instruction specifies a ward operation, the processor writes
bath bytes. When the instruction specifies a byte operation, the processor uses an internal AO bit to
determine which byte to write and then issues the data strobe required for that byte. For byte operations,
when the AO bit equals zero, the upper data strobe is issued. When the AO bit equals one, the lower
data strobe is issued.
Table 2-10.
Addressing Modes
Addressing Modes
Syntax
Register direct addressing
Data register direct
Address register direct
Dn
An
Absolute data addressing
Absolute short
Absolute long
xxx.W
xxx.L
Program counter relative addressing
Relative with offset
Relative with index offset
d16 (PC)
d8 (PC, Xn)
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