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| 型号： | TSX68C000MCB/C12.5A |
| 厂商： | E2V TECHNOLOGIES PLC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 12.5 MHz, MICROPROCESSOR, CDIP64 |
| 封装： | CERAMIC, SDIP-64 |
| 文件页数： | 37/54页 |
| 文件大小： | 901K |
| 代理商： | TSX68C000MCB/C12.5A |
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42
0853B–HIREL–09/07
TS68C000
e2v semiconductors SAS 2007
2.7.5
Processing States
The TS68C000 is always in one of three processing states: normal, exception, or halted.
2.7.5.1
Normal Processing
The normal processing state is that associated with instruction execution; the memory references are to
fetch instructions and operands, and to store results. A special case of normal state is the stopped state
which the processor enters when a stop instruction is executed. In this state, no further references are
made.
2.7.5.2
Exception Processing
The exception processing state is associated with interrupts, trap instructions, tracing, and other excep-
tion conditions. The exception may be internally generated by an instruction or by an unusual condition
arising during the execution of an instruction. Externally, exception processing can be forced by an inter-
rupt, by a bus error, or by a reset. Exception processing is designed to provide an efficient context switch
so that the processor may handle unusual conditions.
2.7.5.3
Halted Processing
The halted processing state is an Indication of catastrophic hardware failure. For example, if during the
exception processing of a bus error another bus errors occurs, the processor assumes that the system is
unusable and halts. Only an external reset can restart a halted processor. Note that a processor in the
stopped state is not in the halted state, nor vice versa.
Asserting the reset and halt line for ten cycles will cause a processor reset, except when VCC is initially
applied to the processor. In this case, an external reset must be applied for least 100 milliseconds.
2.7.6
Interface with EF 6800 Peripherals
Extensive line of EF6800 peripherals are directly compatible with the TS68C000.
Note: It is the own user's responsibility to verify the actual EF 6800 peripheral performances to be com-
patible to the actual used TS68C000 microprocessor performances.
Soma of the EF 6800 peripheral that are particularly useful are:
EF6821: Peripheral lnterface Adapter
EF6840: Programmable Timer Module
EF6850: Asynchronous Communications Interface Adapter
EF6852: Synchronous Serial Data Adapter
EF6854: Advanced Data Link Controller
To interface the synchronous EF 6800 peripherals with the asynchronous TS68C000, the processor
modifies its bus cycle to meet the EF 6800 cycle requirements whenever an EF 6800 device address is
detected. This is possible since both processors use memory mapped 1/0. Figure 2-13 is a flowchart of
the interface operation between the processor and EF 6800 devices.
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