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| 型号： | TSX68C000MCB/C12.5A |
| 厂商： | E2V TECHNOLOGIES PLC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 12.5 MHz, MICROPROCESSOR, CDIP64 |
| 封装： | CERAMIC, SDIP-64 |
| 文件页数： | 4/54页 |
| 文件大小： | 901K |
| 代理商： | TSX68C000MCB/C12.5A |
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12
0853B–HIREL–09/07
TS68C000
e2v semiconductors SAS 2007
Note:
1. Load networks number 1 to 4 as specified in “Test Conditions Specific to the Device” on page 27 (Figure 2-2 and Figure 2-3)
gives the maximum loading for the relevant output.
2.4.4.3
Special Recommended Conditions for CMOS Devices
1.
CMOS Latch-up
The CMOS cell is basically composed of two complementary transistors (a P-channel and an N-chan-
nel), and, in the steady state, only one transistor is turned-on. The active P-channel transistor sources
current when the output is a logic high and presents a high impedance when the output is a logic low.
Thus the overall result is extremely low power consumption because there is no power loss through the
active P.channel transistor. Also since only once transistor is determined by leakage currents.
Because the basic CMOS cell is composed of two complementary transistors, a virtual semiconductor
controlled rectifier (SCR) may be formed when an input exceeds the supply voltage. The SCR that is
formed by this high input causes the device to become "Iatched" in a mode that may result in excessive
current drain and eventual destruction of the device. Although the device is Implemented with input pro-
tection diodes, care should be exercised to ensure that the maximum input voltages specification is not
exceeded tram voltage transients; others may require no additional circuitry.
Table 2-2.
Recommended Condition of Use
Symbol
Parameter
Operating Range
Model
Min
Max
Unit
VCC
Supply voltage
All
4.5
5.5
V
IL
Low level input voltage
All
0
0.8
V
VIH
High level input voltage (see also “Package” on page 10)All
2.0
VCC
V
TCASE
Operating temperature
All
-55
+125
°C
R
L
Value of output load resistance
All
CL
Output loading capacitance
All
pF
tr(c)
Clock rise time (see Figure 2-1)All
10
ns
t
f(c)
Clock fall time (see Figure 2-1)All
10
ns
fC
Clock frequency (see Figure 2-1)
TS68C000-8
4.0
8.0
MHz
TS68C000-10
4.0
10.0
MHz
TS68C000-12
4.0
12.5
MHz
tCYC
Clock time (see Figure 2-1)
TS68C000-8
125
250
ns
TS68C000-10
100
250
ns
TS68C000-12
80
250
ns
t
W(CL)
Clock pulse width low (see Figure 2-1)
TS68C000-8
55
125
ns
TS68C000-10
45
125
ns
TS68C000-12
35
125
ns
t
W(CH)
Cycle pulse width high (see Figure 2-1)
TS68C000-8
55
125
ns
TS68C000-10
45
125
ns
TS68C000-12
35
125
ns
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