- 您现在的位置：买卖IC网 > PDF目录3974 > UPD44647366AF5-E25-FQ1 (Renesas Electronics America)SRAM QDRII 72MBIT 165-PBGA PDF资料下载
参数资料
| 型号： | UPD44647366AF5-E25-FQ1 |
| 厂商： | Renesas Electronics America |
| 文件页数： | 13/42页 |
| 文件大小： | 0K |
| 描述： | SRAM QDRII 72MBIT 165-PBGA |
| 标准包装： | 1 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 同步，QDR II+ |
| 存储容量： | 72M（2M x 36） |
| 速度： | 400MHz |
| 接口： | 并联 |
| 电源电压： | 1.7 V ~ 1.9 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 165-LBGA |
| 供应商设备封装： | 165-PBGA（13x15） |
| 包装： | 散装 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页当前第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页
μ PD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
Truth Table
2.0 Clock Cycles Read Latency
[ μ PD44647094A-A], [ μ PD44647184A-A], [ μ PD44647364A-A]
WRITE cycle
Operation
CLK
L → H
R#
H
W#
L
Data in
D or Q
Load address, input write data on two
consecutive K and K# rising edge
READ cycle
Load address, read data on two
consecutive K and K# rising edge
NOP (No operation)
Clock stop
L → H
L → H
Stopped
L
H
X
X
H
X
Input data
Input clock
Data out
Output data
Output clock
D = X, Q = High-Z
Previous state
D A (A+0)
K(t+1) ↑
Q A (A+0)
K(t+2) ↑
D A (A+1)
K#(t+1) ↑
Q A (A+1)
K#(t+2) ↑
D A (A+2)
K(t+2) ↑
Q A (A+2)
K(t+3) ↑
D A (A+3)
K#(t+2) ↑
Q A (A+3)
K#(t+3) ↑
2.5 Clock Cycles Read Latency
[ μ PD44647096A-A], [ μ PD44647186A-A], [ μ PD44647366A-A]
WRITE cycle
Operation
CLK
L → H
R#
H
W#
L
Data in
D or Q
Load address, input write data on two
consecutive K and K# rising edge
READ cycle
Load address, read data on two
consecutive K and K# rising edge
NOP (No operation)
Clock stop
L → H
L → H
Stopped
L
H
X
X
H
X
Input data
Input clock
Data out
Output data
Output clock
D = X, Q = High-Z
Previous state
D A (A+0)
K(t+1) ↑
Q A (A+0)
K#(t+2) ↑
D A (A+1)
K#(t+1) ↑
Q A (A+1)
K(t+3) ↑
D A (A+2)
K(t+2) ↑
Q A (A+2)
K#(t+3) ↑
D A (A+3)
K#(t+2) ↑
Q A (A+3)
K(t+4) ↑
Remarks
Remarks listed below are for both products with 2.0 and 2.5 Clock Cycles Read Latency.
1. H : HIGH, L : LOW, × : don’t care, ↑ : rising edge.
2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at K and K# rising edges.
3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of
K. All control inputs are registered during the rising edge of K.
4. This device contains circuitry that ensure the outputs to be in high impedance during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. It is recommended that K = K# when clock is stopped. This is not essential but permits most rapid restart
by overcoming transmission line charging symmetrically.
7. If R# was LOW to initiate the previous cycle, this signal becomes a don't care for this WRITE operation
however it is strongly recommended that this signal is brought HIGH as shown in the truth table.
8. W# during write cycle and R# during read cycle were HIGH on previous K clock rising edge. Initiating
consecutive READ or WRITE operations on consecutive K clock rising edges is not permitted. The
device will ignore the second request.
Data Sheet M19962EJ2V0DS
11
相关PDF资料 |
PDF描述 |
|---|---|
| MC7448HX1400NC | IC MPU RISC 32BIT 360-FCCBGA |
| UPD44647186AF5-E25-FQ1-A | SRAM QDRII 72MBIT 165-PBGA |
| UPD44647186AF5-E25-FQ1 | SRAM QDRII 72MBIT 165-PBGA |
| UPD44646363AF5-E25-FQ1-A | SRAM DDRII 72MBIT 165-PBGA |
| UPD44646363AF5-E25-FQ1 | SRAM DDRII 72MBIT 165-PBGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| UPD44647366AF5-E25-FQ1-A | 功能描述:SRAM QDRII 72MBIT 165-PBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:3,000 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:1.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOIC 包装:带卷 (TR) |
| UPD446C-2L | 制造商:NEC Electronics Corporation 功能描述:2K X 8 STANDARD SRAM, 200 ns, PDIP24 |
| UPD446G-20L | 制造商:NEC Electronics Corporation 功能描述:2K X 8 STANDARD SRAM, 200 ns, PDFP24 |
| UPD45128163G5 | 制造商:Renesas Electronics Corporation 功能描述:128 MBIT SDRAM |
| UPD45128163G5-A75-9JF | 制造商:Elpida Memory Inc 功能描述:8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
发布紧急采购，3分钟左右您将得到回复。