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参数资料
| 型号： | UPD44647366AF5-E25-FQ1 |
| 厂商： | Renesas Electronics America |
| 文件页数： | 3/42页 |
| 文件大小： | 0K |
| 描述： | SRAM QDRII 72MBIT 165-PBGA |
| 标准包装： | 1 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 同步，QDR II+ |
| 存储容量： | 72M（2M x 36） |
| 速度： | 400MHz |
| 接口： | 并联 |
| 电源电压： | 1.7 V ~ 1.9 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 165-LBGA |
| 供应商设备封装： | 165-PBGA（13x15） |
| 包装： | 散装 |
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DATA SHEET
MOS INTEGRATED CIRCUIT
μ PD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
72M-BIT QDR TM II+ SRAM
2.0 & 2.5 CLOCK CYCLES READ LATENCY
4-WORD BURST OPERATION
Description
The μ PD44647094A-A and μ PD44647096A-A are 8,388,608-word by 9-bit, the μ PD44647184A-A and μ PD44647186A-A
are 4,194,304-word by 18-bit and the μ PD44647364A-A and μ PD44647366A-A are 2,097,152-word by 36-bit synchronous
quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.
The μ PD44647xx4A-A is for 2.0 clock cycles and the μ PD44647xx6A-A is for 2.5 clock cycles read latency. The
μ PD44647094A-A, μ PD44647096A-A, μ PD44647184A-A, μ PD44647186A-A, μ PD44647364A-A and μ PD44647366A-
A integrate unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock
pair (K and K#) are latched on the positive edge of K and K#.
These products are suitable for application which require synchronous operation, high speed, low voltage, high density
and wide bit configuration.
These products are packaged in 165-pin PLASTIC BGA.
Features
? 1.8 ± 0.1 V power supply
? 165-pin PLASTIC BGA (15 x 17)
? HSTL interface
? DLL/PLL circuitry for wide output data valid window and future frequency scaling
? Separate independent read and write data ports with concurrent transactions
? 100% bus utilization DDR READ and WRITE operation
? Four-tick burst for reduced address frequency
? Two input clocks (K and K#) for precise DDR timing at clock rising edges only
? Two Echo clocks (CQ and CQ#)
? Data Valid pin (QVLD) supported
? Read latency : 2.0 & 2.5 clock cycles (Not selectable by user)
? Internally self-timed write control
? Clock-stop capability. Normal operation is restored in 20 μ s after clock is resumed.
? User programmable impedance output (35 to 70 Ω )
? Fast clock cycle time : 2.5 ns (400 MHz) for 2.0 clock cycles read latency,
2.0 ns (500 MHz) for 2.5 clock cycles read latency
? Simple control logic for easy depth expansion
? JTAG 1149.1 compatible test access port
? On-Die Termination (ODT) for better signal quality (Selectable ON/OFF by user)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M19962EJ2V0DS00 (2nd edition)
Date Published March 2010
Printed in Japan
2009, 2010
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| UPD44647186AF5-E25-FQ1-A | SRAM QDRII 72MBIT 165-PBGA |
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| UPD44646363AF5-E25-FQ1-A | SRAM DDRII 72MBIT 165-PBGA |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| UPD44647366AF5-E25-FQ1-A | 功能描述:SRAM QDRII 72MBIT 165-PBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:3,000 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:1.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOIC 包装:带卷 (TR) |
| UPD446C-2L | 制造商:NEC Electronics Corporation 功能描述:2K X 8 STANDARD SRAM, 200 ns, PDIP24 |
| UPD446G-20L | 制造商:NEC Electronics Corporation 功能描述:2K X 8 STANDARD SRAM, 200 ns, PDFP24 |
| UPD45128163G5 | 制造商:Renesas Electronics Corporation 功能描述:128 MBIT SDRAM |
| UPD45128163G5-A75-9JF | 制造商:Elpida Memory Inc 功能描述:8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
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