参数资料
型号: UPD44647366AF5-E25-FQ1
厂商: Renesas Electronics America
文件页数: 14/42页
文件大小: 0K
描述: SRAM QDRII 72MBIT 165-PBGA
标准包装: 1
格式 - 存储器: RAM
存储器类型: SRAM - 同步,QDR II+
存储容量: 72M(2M x 36)
速度: 400MHz
接口: 并联
电源电压: 1.7 V ~ 1.9 V
工作温度: 0°C ~ 70°C
封装/外壳: 165-LBGA
供应商设备封装: 165-PBGA(13x15)
包装: 散装
μ PD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
Byte Write Operation
[ μ PD44647094A-A], [ μ PD44647096A-A]
Operation
Write D0 to D8
Write nothing
K
L → H
L → H
K#
L → H
L → H
BW0#
0
0
1
1
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# can be altered for any portion of the BURST WRITE
operation provided that the setup and hold requirements are satisfied.
[ μ PD44647184A-A], [ μ PD44647186A-A]
Operation
Write D0 to D17
Write D0 to D8
Write D9 to D17
Write nothing
K
L → H
L → H
L → H
L → H
K#
L → H
L → H
L → H
L → H
BW0#
0
0
0
0
1
1
1
1
BW1#
0
0
1
1
0
0
1
1
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
[ μ PD44647364A-A], [ μ PD44647366A-A]
Operation
Write D0 to D35
Write D0 to D8
Write D9 to D17
Write D18 to D26
Write D27 to D35
Write nothing
K
L → H
L → H
L → H
L → H
L → H
L → H
K#
L → H
L → H
L → H
L → H
L → H
L → H
BW0#
0
0
0
0
1
1
1
1
1
1
1
1
BW1#
0
0
1
1
0
0
1
1
1
1
1
1
BW2#
0
0
1
1
1
1
0
0
1
1
1
1
BW3#
0
0
1
1
1
1
1
1
0
0
1
1
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# to BW3# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
12
Data Sheet M19962EJ2V0DS
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