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参数资料
| 型号： | V59C1512164QALP37I |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, PBGA92 |
| 封装： | GREEN, FBGA-92 |
| 文件页数： | 2/79页 |
| 文件大小： | 1028K |
| 代理商： | V59C1512164QALP37I |
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V59C1G01(408/808/168)QA Rev. 1.3 June 2008
ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QA
DDR2 SDRAM Mode Register Set (MRS)
The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls
CAS latency, burst length, burst sequence, test mode, DLL reset, tWR and various vendor specific options to
make DDR2 SDRAM useful for various applications. The default value of the mode register is not defined,
therefore the mode register must be written after power-up for proper operation. The mode register is written
by asserting low on CS, RAS, CAS, WE, BA0 and BA1, while controlling the state of address pins A0 ~ A15.
The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the mode reg-
ister. The mode register set command cycle time (tMRD) is required to complete the write operation to the
mode register. The mode register contents can be changed using the same command and clock cycle
requirements during normal operation as long as all banks are in the precharge state. The mode register is
divided into various fields depending on functionality. Burst length is defined by A0 ~ A2 with options of 4 and
8 bit burst lengths. The burst length decodes are compatible with DDR SDRAM. Burst address sequence type
is defined by A3, CAS latency is defined by A4 ~ A6. The DDR2 doesn’t support half clock latency mode. A7
is used for test mode. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Write recov-
ery time tWR is defined by A9 ~ A11. Refer to the table for specific codes.
Address Field
CAS Laten cy
A6
A5
A4
Latenc y
0
Reserved
0
1
Reserved
0
1
0
Reserved
01
1
3
10
0
4
10
1
5
1
0
6
11
1
7
A7
mode
0
Normal
1Test
A3
Burst T ype
0
Sequential
1
Interleave
A8
DLL Re set
0No
1Yes
Mode Register
BA1
BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
TM
CAS Latency
BT
DLL
0*1
WR
Write reco very for au toprecharg e
A11
A10
A9
WR(cycle s)
0
Reserved
00
1
2
01
0
3
01
1
4
10
0
5
10
1
6
11
0
7
1
Reserved
A15*1~A13
0
Burst Length
Burs t Le ng th
A2
A1
A0
BL
01
0
4
01
1
8
*1 A14 and A15 is reserved for future usage.
*2 : WR(write recovery for autoprecharge) min is determined by tCK max and WR max is determined by tCK min.
WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up a non-integer value to
the next integer (WR[cycles] = tWR(ns)/tCK(ns)). The mode register must be programmed to this value. This is
also used with tRP to determine tDAL.
BA1
BA0
MRS mode
00
MRS
01
EMRS(1)
1
0
EMRS(2)
1
EMRS(3): Reserved
*2
A12
PD
A12
Active p ower
do wn exit time
0
Fast exit(use tXARD)
1
Slow exit(use tXARDS)
BA2
0
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相关代理商/技术参数 |
参数描述 |
|---|---|
| V59C1512164QDJ25 | 制造商:ProMOS 功能描述:32M*16 DDRII, 1.8V, BGA, 400MHz, Green Part 制造商:ProMOS Technologies INC. 功能描述:32M*16 DDRII, 1.8V, BGA, 400MHz, Green Part |
| V59C1512164QDJ25A | 制造商:ProMOS 功能描述:32M*16 DDRII, 1.8V, BGA, 800MHz, Green Part, CL6 制造商:ProMOS Technologies INC. 功能描述:32M*16 DDRII, 1.8V, BGA, 800MHz, Green Part, CL6 |
| V59C1512164QDJ25I | 制造商:ProMOS 功能描述:32M*16 DDRII, 1.8V, BGA, 333MHz, Green Part, 制造商:ProMOS Technologies INC. 功能描述:32M*16 DDRII, 1.8V, BGA, 333MHz, Green Part, |
| V59C1512164QDJ3 | 制造商:ProMOS 功能描述:32M*16 DDRII, 1.8V, BGA, 333MHz, Green Part 制造商:ProMOS Technologies INC. 功能描述:32M*16 DDRII, 1.8V, BGA, 333MHz, Green Part |
| V59C1512164QDJ3I | 制造商:ProMOS 功能描述:32M*16 DDRII, 1.8V, BGA, 333MHz, Green Part, 制造商:ProMOS Technologies INC. 功能描述:32M*16 DDRII, 1.8V, BGA, 333MHz, Green Part, |
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