- 您现在的位置：买卖IC网 > PDF目录202172 > V59C1512164QALP37I (PROMOS TECHNOLOGIES INC) 32M X 16 DDR DRAM, PBGA92 PDF资料下载
参数资料
| 型号： | V59C1512164QALP37I |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, PBGA92 |
| 封装： | GREEN, FBGA-92 |
| 文件页数： | 37/79页 |
| 文件大小： | 1028K |
| 代理商： | V59C1512164QALP37I |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页当前第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页
42
V59C1G01(408/808/168)QA Rev. 1.3 June 2008
ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QA
Auto-Precharge Operation
Before a new row in an active bank can be opened, the active bank must be precharged using either the Pre-
charge Command or the Auto-Precharge function. When a Read or a Write Command is given to the DDR2
SDRAM, the CAS timing accepts one extra address, column address A10, to allow the active bank to auto-
matically begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is low
when the Read or Write Command is issued, then normal Read or Write burst operation is executed and the
bank remains active at the completion of the burst sequence. If A10 is high when the Read or Write Com-
mand is issued, then the Auto-Precharge function is enabled. During Auto-Precharge, a Read Command will
execute as normal with the exception that the active bank will begin to precharge internally on the rising edge
which is CAS Latency (CL) clock cycles before the end of the read burst. Auto-Precharge is also implemented
for Write Commands.The precharge operation engaged by the Auto-Precharge command will not begin until
the last datga of the write burst sequence is properly stored in the memory array. This feature allows the pre-
charge operation to be partially or completely hidden during burst read cycles (dependent upon CAS Latency)
thus improving system performance for random data access. The RAS lockout circuit internally delays the
Precharge operation until the array restore operation has been completed so that the Auto-Precharge com-
mand may be issied with any read or write command.
Burst Read with Auto-Precharge
If A10 is high when a Read Command is issued, the Read with Auto-Precharge function is engaged. The
DDR2 SDRAM starts an Auto-Precharge operation on the rising edge which is (AL + BL/2) cycles later from
the Read with AP command if tRAS(min) and tRTP are satisfied. If tRAS(min) is not satisfied at the edge, the
start point of Auto-Precharge operation will be delayed until tRAS(min) is satisfied. If tRTP(min) is not satis-
fied at the edge, the start point of Auto-precharge operation will be delayed until tRTP(min) is satisfied.
In case the internal precharge is pushed out by tRTP, tRP starts at the point where the internal precharge
happens (not at the next rising clock edge after this event). So for BL = 4 the minimum time from Read with
Auto-Precharge to the next Activate command becomes AL + tRTP + tRP. For BL = 8 the time from Read with
Auto-Precharge to the next Activate command is AL + 2 + tRTP + tRP. Note that both parameters tRTP and
tRP have to be rounded up to the next integer value. In any event internal precharge does not start earlier
than two clocks after the last 4-bit prefetch.
A new bank active (command) may be issued to the same bank if the following two conditions are satisfied
simultaneously:
(1) The RAS precharge time (tRP) has been satisfied from the clock at which the Auto-Precharge begins.
(2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.
相关PDF资料 |
PDF描述 |
|---|---|
| V59C1512164QAUJ5I | 32M X 16 DDR DRAM, PBGA92 |
| V59C1512164QAUP19AH | 32M X 16 DDR DRAM, PBGA92 |
| V59C1512168QALP25E | 32M X 16 DDR DRAM, BGA92 |
| V59C1512168QAUF37I | 32M X 16 DDR DRAM, PBGA92 |
| V59C1512168QAUJ19H | 32M X 16 DDR DRAM, PBGA92 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| V59C1512164QDJ25 | 制造商:ProMOS 功能描述:32M*16 DDRII, 1.8V, BGA, 400MHz, Green Part 制造商:ProMOS Technologies INC. 功能描述:32M*16 DDRII, 1.8V, BGA, 400MHz, Green Part |
| V59C1512164QDJ25A | 制造商:ProMOS 功能描述:32M*16 DDRII, 1.8V, BGA, 800MHz, Green Part, CL6 制造商:ProMOS Technologies INC. 功能描述:32M*16 DDRII, 1.8V, BGA, 800MHz, Green Part, CL6 |
| V59C1512164QDJ25I | 制造商:ProMOS 功能描述:32M*16 DDRII, 1.8V, BGA, 333MHz, Green Part, 制造商:ProMOS Technologies INC. 功能描述:32M*16 DDRII, 1.8V, BGA, 333MHz, Green Part, |
| V59C1512164QDJ3 | 制造商:ProMOS 功能描述:32M*16 DDRII, 1.8V, BGA, 333MHz, Green Part 制造商:ProMOS Technologies INC. 功能描述:32M*16 DDRII, 1.8V, BGA, 333MHz, Green Part |
| V59C1512164QDJ3I | 制造商:ProMOS 功能描述:32M*16 DDRII, 1.8V, BGA, 333MHz, Green Part, 制造商:ProMOS Technologies INC. 功能描述:32M*16 DDRII, 1.8V, BGA, 333MHz, Green Part, |
发布紧急采购，3分钟左右您将得到回复。