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| 型号： | V59C1512164QALP37I |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, PBGA92 |
| 封装： | GREEN, FBGA-92 |
| 文件页数： | 31/79页 |
| 文件大小： | 1028K |
| 代理商： | V59C1512164QALP37I |
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37
ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QA
V59C1G01(408/808/168)QA Rev. 1.3 June 2008
Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Com-
mand is triggered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Pre-
charge Command can be used to precharge each bank independently or all banks simultaneously. Three
address bits A10, BA1 and BA0 are used to define which bank to precharge when the command is issued.
Bank Selection for Precharge by Address Bits
A10
BA0
BA1
Precharge
Bank(s)
LOW
Bank 0 only
LOW
HIGH
Bank 1 only
LOW
HIGH
LOW
Bank 2 only
LOW
HIGH
Bank 3 only
BA2
LOW
HIGH
LOW
Bank 4 only
A10
BA0
BA1
Precharge
Bank(s)
LOW
Bank 6 only
LOW
HIGH
Bank 7 only
All Banks
BA2
Bank 5 only
HIGH
LOW
HIGH
Don't Care
Burst Read Operation Followed by a Precharge
The following rules apply as long as the tRTP timing parameter - Internal Read to Precharge Command delay
time - is less or equal two clocks, which is the case for operating frequencies less or equal 266 Mhz (DDR2
400 and 533 speed sorts):
Minimum Read to Precharge command spacing to the same bank = AL + BL/2 clocks. For the earliest possi-
ble precharge, the precharge command may be issued on the rising edge which is “Additive Latency (AL) +
BL/2 clocks” after a Read Command, as long as the minimum tRAS timing is satisfied.
A new bank active command may be issued to the same bank if the following two conditions are satisfied
simultaneously:
(1) The RAS precharge time (tRP) has been satisfied from the clock at which the precharge begins.
(2) The RAS cycle time (tRCmin) from the previous bank activation has been satisfied.
For operating frequencies higher than 266 MHz, tRTP becomes > 2 clocks and one additional clock cycle
has to be added for the minimum Read to Precharge command spacing, which now becomes AL + BL/2 + 1
clocks.
相关PDF资料 |
PDF描述 |
|---|---|
| V59C1512164QAUJ5I | 32M X 16 DDR DRAM, PBGA92 |
| V59C1512164QAUP19AH | 32M X 16 DDR DRAM, PBGA92 |
| V59C1512168QALP25E | 32M X 16 DDR DRAM, BGA92 |
| V59C1512168QAUF37I | 32M X 16 DDR DRAM, PBGA92 |
| V59C1512168QAUJ19H | 32M X 16 DDR DRAM, PBGA92 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| V59C1512164QDJ25 | 制造商:ProMOS 功能描述:32M*16 DDRII, 1.8V, BGA, 400MHz, Green Part 制造商:ProMOS Technologies INC. 功能描述:32M*16 DDRII, 1.8V, BGA, 400MHz, Green Part |
| V59C1512164QDJ25A | 制造商:ProMOS 功能描述:32M*16 DDRII, 1.8V, BGA, 800MHz, Green Part, CL6 制造商:ProMOS Technologies INC. 功能描述:32M*16 DDRII, 1.8V, BGA, 800MHz, Green Part, CL6 |
| V59C1512164QDJ25I | 制造商:ProMOS 功能描述:32M*16 DDRII, 1.8V, BGA, 333MHz, Green Part, 制造商:ProMOS Technologies INC. 功能描述:32M*16 DDRII, 1.8V, BGA, 333MHz, Green Part, |
| V59C1512164QDJ3 | 制造商:ProMOS 功能描述:32M*16 DDRII, 1.8V, BGA, 333MHz, Green Part 制造商:ProMOS Technologies INC. 功能描述:32M*16 DDRII, 1.8V, BGA, 333MHz, Green Part |
| V59C1512164QDJ3I | 制造商:ProMOS 功能描述:32M*16 DDRII, 1.8V, BGA, 333MHz, Green Part, 制造商:ProMOS Technologies INC. 功能描述:32M*16 DDRII, 1.8V, BGA, 333MHz, Green Part, |
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