参数资料
型号: V59C1512164QALP37I
厂商: PROMOS TECHNOLOGIES INC
元件分类: DRAM
英文描述: 32M X 16 DDR DRAM, PBGA92
封装: GREEN, FBGA-92
文件页数: 46/79页
文件大小: 1028K
代理商: V59C1512164QALP37I
50
V59C1G01(408/808/168)QA Rev. 1.3 June 2008
ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QA
Power-Down
Power-down is synchronously entered when CKE is registered low along with NOP or Deselect command.
No read or write operation may be in progress when CKE goes low. These operations are any of the follow-
ing: read burst or write burst and recovery. CKE is allowed to go low while any of other operations such as
row activation, precharge or autoprecharge, mode register or extended mode register command time, or
autorefresh is in progress. The DLL should be in a locked state when power-down is entered. Otherwise DLL
should be reset after exiting power-down mode for proper read operation.
If power-down occurs when all banks are precharged, this mode is referred to as Precharge Power-down; if
power-down occurs when there is a row active in any bank, this mode is referred to as Active Power-down.
For Active Power-down two different power saving modes can be selected within the MRS register, address
bit A12. When A12 is set to “low” this mode is referred as “standard active power-down mode” and a fast
power-down exit timing defined by the tXARD timing parameter can be used. When A12 is set to “high” this
mode is referred as a power saving “low power active power-down mode”. This mode takes longer to exit
from the power-down mode and the tXARDS timing parameter has to be satisfied.
Entering power-down deactivates the input and output buffers, excluding CK, CK, ODT and CKE. Also the
DLL is disabled upon entering precharge power-down or slow exit active power-down, but the DLL is kept
enabled during fast exit active power-down. In power-down mode, CKE low and a stable clock signal must be
maintained at the inputs of the DDR2 SDRAM, and all other input signals are “Don’t Care”. Power-down dura-
tion is limited by 9 times tREFI of the device.
The power-down state is synchronously exited when CKE is registered high (along with a NOP or Deselect
command). A valid, executable command can be applied with power-down exit latency, tXP, tXARD or
tXARDS, after CKE goes high. Power-down exit latencies are defined in the AC spec table of this data sheet.
Power-Down Entry
Active Power-down mode can be entered after an activate command. Precharge Power-down mode can be
entered after a precharge, precharge-all or internal precharge command. It is also allowed to enter power-
mode after an Auto-Refresh command or MRS / EMRS command when tMRD is satisfied.
Active Power-down mode entry is prohibited as long as a Read Burst is in progress, meaning CKE should be
kept high until the burst operation is finished. Therefore Active Power-Down mode entry after a Read or Read
with Auto-Precharge command is allowed after RL + BL/2 is satisfied.
Active Power-down mode entry is prohibited as long as a Write Burst and the internal write recovery is in
progress. In case of a write command, active power-down mode entry is allowed when WL + BL/2 + tWTR is
satisfied.
In case of a write command with auto-precharge, power-down mode entry is allowed after the internal pre-
charge command has been executed, which is WL + BL/2 + WR starting from the write with auto-precharge
command. In case the DDR2 SDRAM enters the Precharge Power-down mode.
相关PDF资料
PDF描述
V59C1512164QAUJ5I 32M X 16 DDR DRAM, PBGA92
V59C1512164QAUP19AH 32M X 16 DDR DRAM, PBGA92
V59C1512168QALP25E 32M X 16 DDR DRAM, BGA92
V59C1512168QAUF37I 32M X 16 DDR DRAM, PBGA92
V59C1512168QAUJ19H 32M X 16 DDR DRAM, PBGA92
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