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参数资料
| 型号： | V59C1512164QALP37I |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, PBGA92 |
| 封装： | GREEN, FBGA-92 |
| 文件页数： | 44/79页 |
| 文件大小： | 1028K |
| 代理商： | V59C1512164QALP37I |
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49
ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QA
V59C1G01(408/808/168)QA Rev. 1.3 June 2008
Self-Refresh Command
The Self-Refresh command can be used to retain data, even if the rest of the system is powered down.
When in the Self-Refresh mode, the DDR2 SDRAM retains data without external clocking.
The DDR2 SDRAM device has a built-in timer to accommodate Self-Refresh operation. The Self-Refresh
Command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock.
ODT must be turned off before issuing Self Refresh command, by either driving ODT pin low or using EMRS
command. Once the command is registered, CKE must be held low to keep the device in Self-Refresh mode.
When the DDR2 SDRAM has entered Self-Refresh mode all of the external control signals, except CKE, are
disabled. The clock is internally disabled during Self-Refresh Operation to save power. The user may change
the external clock frequency or halt the external clock one clock after Self-Refresh entry is registered, how-
ever, the clock must be restarted and stable before the device can exit Self-Refresh operation. Once Self-
Refresh Exit command is registered, a delay equal or longer than the tXSNR or tXSRD must be satisfied
before a valid command can be issued to the device. CKE must remain high for the entire Self-Refresh exit
period (tXSNR or tXSRD) for proper operation. NOP or DESELECT commands must be registered on each
positive clock edge during the Self-Refresh exit interval. Since the ODT function is not supported during Self-
Refresh operation, ODT has to be turned off tAOFD before entering Self-Refresh Mode and can be turned on
again when the tXSRD timing is satisfied.
* = Device must be in the “All banks idle” state to entering Self Refresh mode.
ODT must be turned off prior to entering Self Refresh mode.
tXSRD has to be satisfied for a Read or a Read with Auto-Precharge command.
tXSNR has to be satisfied for any command except a Read or a Read with Auto-Precharge command.
CK/CK
T1
T3
T2
CK/CK may
be halted
CK/CK must
be stable
CKE
>=tXSRD
>= tXSNR
Tn
Tr
Tm
T5
T4
tRP*
tis
tAOFD
CMD
Self Refresh
Entry
NOP
Non-Read
Command
Read
Command
T0
tis
ODT
相关PDF资料 |
PDF描述 |
|---|---|
| V59C1512164QAUJ5I | 32M X 16 DDR DRAM, PBGA92 |
| V59C1512164QAUP19AH | 32M X 16 DDR DRAM, PBGA92 |
| V59C1512168QALP25E | 32M X 16 DDR DRAM, BGA92 |
| V59C1512168QAUF37I | 32M X 16 DDR DRAM, PBGA92 |
| V59C1512168QAUJ19H | 32M X 16 DDR DRAM, PBGA92 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| V59C1512164QDJ25 | 制造商:ProMOS 功能描述:32M*16 DDRII, 1.8V, BGA, 400MHz, Green Part 制造商:ProMOS Technologies INC. 功能描述:32M*16 DDRII, 1.8V, BGA, 400MHz, Green Part |
| V59C1512164QDJ25A | 制造商:ProMOS 功能描述:32M*16 DDRII, 1.8V, BGA, 800MHz, Green Part, CL6 制造商:ProMOS Technologies INC. 功能描述:32M*16 DDRII, 1.8V, BGA, 800MHz, Green Part, CL6 |
| V59C1512164QDJ25I | 制造商:ProMOS 功能描述:32M*16 DDRII, 1.8V, BGA, 333MHz, Green Part, 制造商:ProMOS Technologies INC. 功能描述:32M*16 DDRII, 1.8V, BGA, 333MHz, Green Part, |
| V59C1512164QDJ3 | 制造商:ProMOS 功能描述:32M*16 DDRII, 1.8V, BGA, 333MHz, Green Part 制造商:ProMOS Technologies INC. 功能描述:32M*16 DDRII, 1.8V, BGA, 333MHz, Green Part |
| V59C1512164QDJ3I | 制造商:ProMOS 功能描述:32M*16 DDRII, 1.8V, BGA, 333MHz, Green Part, 制造商:ProMOS Technologies INC. 功能描述:32M*16 DDRII, 1.8V, BGA, 333MHz, Green Part, |
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