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参数资料
| 型号： | V59C1512164QALP37I |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, PBGA92 |
| 封装： | GREEN, FBGA-92 |
| 文件页数： | 73/79页 |
| 文件大小： | 1028K |
| 代理商： | V59C1512164QALP37I |
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75
ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QA
V59C1G01(408/808/168)QA Rev. 1.3 June 2008
Notes for Electrical Characteristics & AC Timing
1. Input slew rate is 1 V/ns and AC timings are guarantedd for linear signal transitions.
For other slew rates see the derating tables on the next pages.
2. The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross:the DQS /
DQS input reference level is the crosspoint when in differential strobe mode; the input reference level for signals
other than CK/CK, or DQS / DQS is VREF.
3. Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x
VDDQ is recognized as LOW.
4. The output timing reference voltage level is VTT.
5. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the
device (i.e. this value can be greater than the minimum specification limits for tCL and tCH.
6. For input frequency change during DRAM operation.
7. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not
referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8. These parameters guarantee device timing, but they are not necessarily tested on each device.
9. The specific requirement is that DQS and DQS be valid (HIGH, LOW, or some point on a valid transition) on or before
this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device.
When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previ-
ous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on
tDQSS. When programmed in differential strobe mode, DQS is always the logic complement of DQS except when
both are in high-Z.
10. The maximum limit for this parameter is not a device limit. The device operate with a greater value for this parameter,
but system performance (bus turnaround) degrades accordingly.
11. A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
(Note : tRFC depends on DRAM density)
12. For each of the terms, if not allready an integer, round to the next highest integer. tCK refers to the application clock
period. WR refers to the WR parameter stored in the MRS.
13. tWTR is at least two clocks independent of operation frequency.
14. User can choose two different active power-down modes for additional power saving via MRS address bit A12.
In “standard active power-down mode” (MRS, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low
active power-down mode” (MRS, A12 =”1”) a slow power-down exit timing tXARDS has to be satisfied.
15. Timings are guaranteed with command / address input slew rate of 1.0 V/ns.
16. Timings are guaranteed with data / mask input slew rate of 1.0 V/ns.
17. Timings are guaranteed with CK /CK differential slew rate 2.0 V/ns, and DQS/DQS ( and RDQS/RDQS) differential
slew rate 2.0 V/ns in differential strobe mode.
18. If refresh timing or tDS / tDH is violated, data corruption may occur and the data must be re-written with valid data
before a valid READ can be executed.
19. In all circumstances, tXSNR can be satisfied using tXSNR = tRFC + 10 ns.
20. The tRCD timing parameter is valid for both activate command to read or write command with and without Auto-Pre-
charge. Therefore a separate parameter tRAP for activate command to read or write command with Auto-Precharge
is not neccessary anymore.
21. tRAS(max) is calculated from the maximum amount of time a DDR2 device can operate without a Refresh command
which is equal to 9 * tREFI.
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相关代理商/技术参数 |
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| V59C1512164QDJ25 | 制造商:ProMOS 功能描述:32M*16 DDRII, 1.8V, BGA, 400MHz, Green Part 制造商:ProMOS Technologies INC. 功能描述:32M*16 DDRII, 1.8V, BGA, 400MHz, Green Part |
| V59C1512164QDJ25A | 制造商:ProMOS 功能描述:32M*16 DDRII, 1.8V, BGA, 800MHz, Green Part, CL6 制造商:ProMOS Technologies INC. 功能描述:32M*16 DDRII, 1.8V, BGA, 800MHz, Green Part, CL6 |
| V59C1512164QDJ25I | 制造商:ProMOS 功能描述:32M*16 DDRII, 1.8V, BGA, 333MHz, Green Part, 制造商:ProMOS Technologies INC. 功能描述:32M*16 DDRII, 1.8V, BGA, 333MHz, Green Part, |
| V59C1512164QDJ3 | 制造商:ProMOS 功能描述:32M*16 DDRII, 1.8V, BGA, 333MHz, Green Part 制造商:ProMOS Technologies INC. 功能描述:32M*16 DDRII, 1.8V, BGA, 333MHz, Green Part |
| V59C1512164QDJ3I | 制造商:ProMOS 功能描述:32M*16 DDRII, 1.8V, BGA, 333MHz, Green Part, 制造商:ProMOS Technologies INC. 功能描述:32M*16 DDRII, 1.8V, BGA, 333MHz, Green Part, |
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