参数资料
| 型号： | W947D6HBHX5E |
| 厂商： | Winbond Electronics |
| 文件页数： | 6/60页 |
| 文件大小： | 0K |
| 描述： | IC LPDDR SDRAM 128MBIT 60VFBGA |
| 标准包装： | 312 |
| 格式 - 存储器： | RAM |
| 存储器类型： | 移动 LPDDR SDRAM |
| 存储容量： | 128M（8Mx16） |
| 速度： | 200MHz |
| 接口： | 并联 |
| 电源电压： | 1.7 V ~ 1.95 V |
| 工作温度： | -25°C ~ 85°C |
| 封装/外壳： | 60-TFBGA |
| 供应商设备封装： | 60-VFBGA（8x9） |
| 包装： | 托盘 |
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W947D6HB / W947D2HB
128Mb Mobile LPDDR
4. PIN DESCRIPTION
4.1 Signal Descriptions
SIGNAL NAME
TYPE
FUNCTION
DESCRIPTION
Provide the row address for ACTIVE commands, and the column
address and AUTO PRECHARGE bit for READ/WRITE
A [n : 0]
Input
Address
commands, to select one location out of the memory array in the
respective bank. The address inputs also provide the opcode
during a MODE REGISTER SET command.
A10 is used for Auto Pre-charge Select.
BA0, BA1
DQ0~DQ15 (×16)
DQ0~DQ31 (×32)
Input
I/O
Bank Select
Data Input/
Output
Define to which bank an ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
Data bus: Input / Output.
CS enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS is
CS
Input
Chip Select
registered HIGH. CS provides for external bank selection on
systems with multiple banks. CS is considered part of the
command code.
RAS
Input
Row Address
Strobe
RAS , CAS and WE (along with CS ) define the command
being entered.
CAS
Input
Column Address Referred to RAS
Strobe
WE
Input
Write Enable
Referred to RAS
Input Data Mask: DM is an input mask signal for write data. Input
data is masked when DM is sampled HIGH along with that input
data during a WRITE access. DM is sampled on both edges of
UDM / LDM(x16);
DM0 to DM3 (x32)
Input
Input Mask
DQS. Although DM pins are input-only, the DM loading matches
the DQ and DQS loading.
x16: LDM: DQ0 - DQ7, UDM: DQ8 – DQ15
x32: DM0: DQ0 - DQ7, DM1: DQ8 – DQ15,
DM2: DQ16 – DQ23, DM3: DQ24 – DQ31
CK and CK are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of
CK / CK
Input
Clock Inputs
CK and negative edge of CK .Input and output data is
referenced to the crossing of CK and CK (both directions of
crossing). Internal clock signals are derived from CK/ CK .
Publication Release Date:Jun,17, 2011
- 6 -
Revision A01-003
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W947D6HBHX5I | 制造商:WINBOND 制造商全称:Winbond 功能描述:128Mb Mobile LPDDR |
| W947D6HBHX5I TR | 制造商:Winbond Electronics Corp 功能描述: |
| W947D6HBHX6E | 制造商:Winbond Electronics Corp 功能描述:IC LPDDR SDRAM 128MBIT 60VFBGA |
| W947D6HBHX6G | 制造商:WINBOND 制造商全称:Winbond 功能描述:128Mb Mobile LPDDR |
| W948D2FB | 制造商:WINBOND 制造商全称:Winbond 功能描述:256Mb Mobile LPDDR |
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