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参数资料
| 型号： | W9712G6JB-3 |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | DRAM |
| 英文描述： | 8M X 16 DDR DRAM, 0.45 ns, PBGA84 |
| 封装： | 12.50 X 8 MM, ROHS COMPLIANT, WBGA-84 |
| 文件页数： | 17/86页 |
| 文件大小： | 1027K |
| 代理商： | W9712G6JB-3 |
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W9712G6JB
Publication Release Date: Mar. 15, 2010
- 24 -
Revision A01
CMD
12
3
45
6
78
9
10
11
12
0
-1
CLK /CLK
DQS/DQS
DQ
AL=2
CL=3
WL=RL-1=4
≥ tRCD
RL=AL+CL=5
Dout0
Din0
Active
A-Bank
Read
A-Bank
Write
A-Bank
Din1
Din2
Din3
Dout1 Dout2 Dout3
[AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4, BL = 4]
Figure 14—Example 1: Read followed by a write to the same bank,
where AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4, BL = 4
12
3
4
5
6
7
8
9
10
11
12
0
-1
CL=3
WL=RL-1=2
≥ tRCD
RL=AL+CL=3
AL=0
CMD
CLK/CLK
DQ
Dout0 Dout1 Dout2 Dout3
Din0
Din1
Din2
Din3
Write
A-Bank
Read
A-Bank
Active
A-Bank
DQS/DQS
AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2, BL = 4]
Figure 15—Example 2: Read followed by a write to the same bank,
where AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2, BL = 4
7.4.2
Burst mode operation
Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or
from memory locations (read cycle). The parameters that define how the burst mode will operate are
burst sequence and burst length. The DDR2 SDRAM supports 4 bit and 8 bit burst modes only. For 8
bit burst mode, full interleave address ordering is supported, however, sequential address ordering is
nibble based for ease of implementation. The burst length is programmable and defined by MR A[2:0].
The burst type, either sequential or interleaved, is programmable and defined by MR [A3]. Seamless
burst read or write operations are supported.
Unlike DDR1 devices, interruption of a burst read or writes cycle during BL = 4 mode operation is
prohibited. However in case of BL = 8 mode, interruption of a burst read or write operation is limited to
two cases, reads interrupted by a read, or writes interrupted by a write. (Example timing waveforms
refer to 10.13 and 10.14 Burst read and write interrupt timing diagram in Chapter 10)
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| W986408BH-8N | 8M X 8 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W9712G6KB-25 | 制造商:Winbond Electronics Corp 功能描述:128M DDR2-800, X16 制造商:Winbond Electronics 功能描述:IC MEMORY 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
| W9712G6KB25I | 制造商:Winbond Electronics 功能描述:IC MEMORY 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
| W9712G8JB | 制造商:WINBOND 制造商全称:Winbond 功能描述:4M × 4 BANKS × 8 BIT DDR2 SDRAM |
| W9712G8JB25 | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR2 SDRAM 128M-Bit 16Mx8 1.8V 60-Pin WBGA |
| W9712G8JB25I | 制造商:Winbond Electronics Corp 功能描述:128M DDR2-800, X8, IND TEMP |
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