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参数资料
| 型号： | W9712G6JB-3 |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | DRAM |
| 英文描述： | 8M X 16 DDR DRAM, 0.45 ns, PBGA84 |
| 封装： | 12.50 X 8 MM, ROHS COMPLIANT, WBGA-84 |
| 文件页数： | 3/86页 |
| 文件大小： | 1027K |
| 代理商： | W9712G6JB-3 |
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W9712G6JB
Publication Release Date: Mar. 15, 2010
- 11 -
Revision A01
SDRAM. Burst address sequence type is defined by A3, CAS Latency is defined by A[6:4]. The DDR2
does not support half clock latency mode. A7 is used for test mode. A8 is used for DLL reset. A7 must
be set to LOW for normal MRS operation. Write recovery time WR is defined by A[11:9]. Refer to the
table for specific codes.
DDR2
-6
67
DDR2
-80
0
DD
R2-1
066
DDR2
-8
00
DDR2-
106
6
D
DR2-
667
Note:
1. WR (write recovery for Auto-precharge) min is determined by tCK(avg) max and WR max is determined by tCK(avg) min.
WR[cycles] = RU{ tWR[nS] / tCK(avg)[nS] }, where RU stands for round up. The mode register must be programmed to this
value. This is also used with tRP to determine tDAL.
Figure 2—Mode Register Set (MRS)
7.2.2
Extend Mode Register Set Commands (EMRS)
7.2.2.1
Extend Mode Register Set Command (1), EMR (1)
( CS = "L", RAS = "L", CAS = "L", WE = "L", BA0 = "H", BA1 = "L", A0 to A11 = Register data)
The extended mode register (1) stores the data for enabling or disabling the DLL, output driver
strength, additive latency, ODT, DQS disable, OCD program. The default value of the extended
mode register (1) is not defined, therefore the extended mode register (1) must be programmed during
initialization for proper operation. The DDR2 SDRAM should be in all bank precharge with CKE
already high prior to writing into the extended mode register (1). The mode register set command
cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register (1).
Extended mode register (1) contents can be changed using the same command and clock cycle
requirements during normal operation as long as all banks are in the precharge state. A0 is used for
DLL enable or disable. A1 is used for enabling a reduced strength output driver. A[5:3] determines the
additive latency, A[9:7] are used for OCD control, A10 is used for DQS disable. A2 and A6 are used
for ODT setting.
相关PDF资料 |
PDF描述 |
|---|---|
| W981616CH-5 | 1M X 16 SYNCHRONOUS DRAM, 5.5 ns, PDSO50 |
| W986408AH-10 | 8M X 8 SYNCHRONOUS DRAM, 8 ns, PDSO54 |
| W986408BH-8N | 8M X 8 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| W986416BH-7 | 4M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| WC320240A-AF | WC320240A-FCI-N |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W9712G6KB-25 | 制造商:Winbond Electronics Corp 功能描述:128M DDR2-800, X16 制造商:Winbond Electronics 功能描述:IC MEMORY 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
| W9712G6KB25I | 制造商:Winbond Electronics 功能描述:IC MEMORY 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
| W9712G8JB | 制造商:WINBOND 制造商全称:Winbond 功能描述:4M × 4 BANKS × 8 BIT DDR2 SDRAM |
| W9712G8JB25 | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR2 SDRAM 128M-Bit 16Mx8 1.8V 60-Pin WBGA |
| W9712G8JB25I | 制造商:Winbond Electronics Corp 功能描述:128M DDR2-800, X8, IND TEMP |
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