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参数资料
| 型号： | W9712G6JB-3 |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | DRAM |
| 英文描述： | 8M X 16 DDR DRAM, 0.45 ns, PBGA84 |
| 封装： | 12.50 X 8 MM, ROHS COMPLIANT, WBGA-84 |
| 文件页数： | 4/86页 |
| 文件大小： | 1027K |
| 代理商： | W9712G6JB-3 |
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W9712G6JB
Publication Release Date: Mar. 15, 2010
- 12 -
Revision A01
7.2.2.2
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization,
and upon returning to normal operation after having the DLL disabled. The DLL is automatically
disabled when entering Self Refresh operation and is automatically re-enabled and reset upon exit of
Self Refresh operation. Any time the DLL is enabled (and subsequently reset), 200 clock cycles must
occur before a Read command can be issued to allow time for the internal clock to be synchronized
with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC
or tDQSCK parameters.
BA1
BA0 A12
A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
1
OCD program
BT
Rtt
Address Field
Extended Mode Register (1)
BA1 BA0
MRS mode
0
1
11
MR
EMR (1)
EMR (2)
EMR (3)
A6
A2
0
1
11
WR
Additive Latency
Qoff
0*
1
DQS
Rtt D.I.C DLL
Rtt (nominal)
ODT Disabled
75 ohm
150 ohm
50 ohm*2
0
A0
1
DLL Enable
Enable
Disable
OCD Calibration Program
OCD calibration mode exit; matain setting
Adjust mode*3
OCD Calibration default*4
Drive (1)
Drive (0)
A9
A8
A7
1
00
0
11
1
00
0
Driver impedance adjustment
A12
1
0
Output buffer enabled
Qoff (Optional)*5
Output buffer disabled
A10
1
0
DQS
Enable
Disable
A10
(DQS Enable)
0 (Enable)
1 (Disable)
Strobe Function Matrix
DQS
Hi-z
Output driver
impedance control
Reduced
Normal
A1
0
1
A5
0
1
A4
0
1
0
1
A3
0
1
0
1
0
1
0
Latency
0
3
4
Reserved
1
2
Output Driver Impedance Control
Driver
size
100%
60%
Additive Latency
5
6
DDR2
-/
66
7/
800
DD
R2-
1066
Notes:
1. A11 default is “0 “ RDQS disabled.
2. Optional for DDR2-667, mandatory for DDR2-800 and DDR2-1066.
3. When Adjust mode is issued, AL from previously set value must be applied.
4. After setting to default, OCD calibration mode needs to be exited by setting A9-A7 to 000. Refer to the section 7.2.3 for
detailed information.
5. Output disabled - DQs, LDQS, LDQS , UDQS, UDQS . This feature is used in conjunction with DIMM IDD measurements
when IDDQ is not desired to be included.
Figure 3—EMR (1)
相关PDF资料 |
PDF描述 |
|---|---|
| W981616CH-5 | 1M X 16 SYNCHRONOUS DRAM, 5.5 ns, PDSO50 |
| W986408AH-10 | 8M X 8 SYNCHRONOUS DRAM, 8 ns, PDSO54 |
| W986408BH-8N | 8M X 8 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| W986416BH-7 | 4M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| WC320240A-AF | WC320240A-FCI-N |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W9712G6KB-25 | 制造商:Winbond Electronics Corp 功能描述:128M DDR2-800, X16 制造商:Winbond Electronics 功能描述:IC MEMORY 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
| W9712G6KB25I | 制造商:Winbond Electronics 功能描述:IC MEMORY 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
| W9712G8JB | 制造商:WINBOND 制造商全称:Winbond 功能描述:4M × 4 BANKS × 8 BIT DDR2 SDRAM |
| W9712G8JB25 | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR2 SDRAM 128M-Bit 16Mx8 1.8V 60-Pin WBGA |
| W9712G8JB25I | 制造商:Winbond Electronics Corp 功能描述:128M DDR2-800, X8, IND TEMP |
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