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| 型号： | W9712G6JB-3 |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | DRAM |
| 英文描述： | 8M X 16 DDR DRAM, 0.45 ns, PBGA84 |
| 封装： | 12.50 X 8 MM, ROHS COMPLIANT, WBGA-84 |
| 文件页数： | 23/86页 |
| 文件大小： | 1027K |
| 代理商： | W9712G6JB-3 |
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W9712G6JB
Publication Release Date: Mar. 15, 2010
- 3 -
Revision A01
10.2
Timing of the CLK Signals...................................................................................................................67
10.3
ODT Timing for Active/Standby Mode.................................................................................................68
10.4
ODT Timing for Power Down Mode ....................................................................................................68
10.5
ODT Timing mode switch at entering power down mode....................................................................69
10.6
ODT Timing mode switch at exiting power down mode ......................................................................70
10.7
Data output (read) timing ....................................................................................................................71
10.8
Burst read operation: RL=5 (AL=2, CL=3, BL=4) ................................................................................71
10.9
Data input (write) timing ......................................................................................................................72
10.10
Burst write operation: RL=5 (AL=2, CL=3, WL=4, BL=4)...........................................................72
10.11
Seamless burst read operation: RL = 5 ( AL = 2, and CL = 3, BL = 4) ......................................73
10.12
Seamless burst write operation: RL = 5 ( WL = 4, BL = 4).........................................................73
10.13
Burst read interrupt timing: RL =3 (CL=3, AL=0, BL=8).............................................................74
10.14
Burst write interrupt timing: RL=3 (CL=3, AL=0, WL=2, BL=8) ..................................................74
10.15
Write operation with Data Mask: WL=3, AL=0, BL=4) ...............................................................75
10.16
Burst read operation followed by precharge: RL=4 (AL=1, CL=3, BL=4, tRTP ≤ 2clks) ............76
10.17
Burst read operation followed by precharge: RL=4 (AL=1, CL=3, BL=8, tRTP ≤ 2clks) ............76
10.18
Burst read operation followed by precharge: RL=5 (AL=2, CL=3, BL=4, tRTP ≤ 2clks) ............77
10.19
Burst read operation followed by precharge: RL=6 (AL=2, CL=4, BL=4, tRTP ≤ 2clks) ............77
10.20
Burst read operation followed by precharge: RL=4 (AL=0, CL=4, BL=8, tRTP > 2clks) ............78
10.21
Burst write operation followed by precharge: WL = (RL-1) = 3 ..................................................78
10.22
Burst write operation followed by precharge: WL = (RL-1) = 4 ..................................................79
10.23
Burst read operation with Auto-precharge: RL=4 (AL=1, CL=3, BL=8, tRTP ≤ 2clks) ...............79
10.24
Burst read operation with Auto-precharge: RL=4 (AL=1, CL=3, BL=4, tRTP > 2clks) ...............80
10.25
Burst read with Auto-precharge followed by an activation to the same bank (tRC Limit): RL=5
(AL=2, CL=3, internal tRCD=3, BL=4, tRTP ≤ 2clks).......................................................................................80
10.26
Burst read with Auto-precharge followed by an activation to the same bank (tRP Limit): RL=5
(AL=2, CL=3, internal tRCD=3, BL=4, tRTP ≤ 2clks).......................................................................................81
10.27
Burst write with Auto-precharge (tRC Limit): WL=2, WR=2, BL=4, tRP=3.................................81
10.28
Burst write with Auto-precharge (WR + tRP Limit): WL=4, WR=2, BL=4, tRP=3.......................82
10.29
Self Refresh Timing ...................................................................................................................82
10.30
Active Power Down Mode Entry and Exit Timing.......................................................................83
10.31
Precharged Power Down Mode Entry and Exit Timing..............................................................83
10.32
Clock frequency change in precharge Power Down mode ........................................................84
11.
PACKAGE SPECIFICATION ..............................................................................................................85
Package Outline WBGA-84 (8x12.5 mm
2).......................................................................................................85
12.
REVISION HISTORY ..........................................................................................................................86
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W9712G6KB-25 | 制造商:Winbond Electronics Corp 功能描述:128M DDR2-800, X16 制造商:Winbond Electronics 功能描述:IC MEMORY 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
| W9712G6KB25I | 制造商:Winbond Electronics 功能描述:IC MEMORY 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
| W9712G8JB | 制造商:WINBOND 制造商全称:Winbond 功能描述:4M × 4 BANKS × 8 BIT DDR2 SDRAM |
| W9712G8JB25 | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR2 SDRAM 128M-Bit 16Mx8 1.8V 60-Pin WBGA |
| W9712G8JB25I | 制造商:Winbond Electronics Corp 功能描述:128M DDR2-800, X8, IND TEMP |
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