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| 型号： | W972GG8JB-25I |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | DRAM |
| 英文描述： | 256M X 8 DDR DRAM, 0.4 ns, PBGA60 |
| 封装： | 11 X 11.50 MM, ROHS COMPLIANT, WBGA-60 |
| 文件页数： | 20/86页 |
| 文件大小： | 1466K |
| 代理商： | W972GG8JB-25I |
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W972GG8JB
Publication Release Date: Feb. 18, 2011
- 27 -
Revision A02
7.6
Precharge operation
The Precharge Command is used to precharge or close a bank that has been activated. The
Precharge Command can be used to precharge each bank independently or all banks simultaneously.
Four address bits A10, BA0 and BA1 and BA2 are used to define which bank to precharge when the
command is issued.
Table 4
– Bank selection for precharge by address bits
A10
BA2
BA1
BA0
Precharge Bank(s)
LOW
Bank 0 only
LOW
HIGH
Bank 1 only
LOW
HIGH
LOW
Bank 2 only
LOW
HIGH
Bank 3 only
LOW
HIGH
LOW
Bank 4 only
LOW
HIGH
LOW
HIGH
Bank 5 only
LOW
HIGH
LOW
Bank 6 only
LOW
HIGH
Bank 7 only
HIGH
Don
t Care
Don
t Care
Don
t Care
All Banks
7.6.1
Burst read operation followed by precharge
Minimum Read to Precharge command spacing to the same bank = AL + BL/2 + max(RTP, 2) - 2 clks
For the earliest possible precharge, the precharge command may be issued on the rising edge which
is “Additive Latency (AL) + BL/2 + max(RTP, 2) - 2 clocks” after a Read command. A new bank active
(command) may be issued to the same bank after the RAS precharge time (tRP). A precharge
command cannot be issued until tRAS is satisfied.
The minimum Read to Precharge spacing has also to satisfy a minimum analog time from the rising
clock edge that initiates the last 4-bit prefetch of a Read to Precharge command. This time is called
tRTP (Read to Precharge). For BL = 4 this is the time from the actual read (AL after the Read
command) to Precharge command. For BL = 8 this is the time from AL + 2 clocks after the Read to the
Precharge command. (Example timing waveforms refer to 10.16 to 10.20 Burst read operation
followed by precharge diagram in Chapter 10)
7.6.2
Burst write operation followed by precharge
Minimum Write to Precharge Command spacing to the same bank = WL + BL/2 clks + tWR
For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the
Precharge Command can be issued. This delay is known as a write recovery time (tWR) referenced
from the completion of the burst write to the precharge command. No Precharge command should be
issued prior to the tWR delay. (Example timing waveforms refer to 10.21 to 10.22 Burst write operation
followed by precharge diagram in Chapter 10)
7.7
Auto-precharge operation
Before a new row in an active bank can be opened, the active bank must be precharged using either
the Precharge command or the Auto-precharge function. When a Read or a Write command is given
to the DDR2 SDRAM, the
CAS timing accepts one extra address, column address A10, to allow the
active bank to automatically begin precharge at the earliest possible moment during the burst read or
write cycle. If A10 is LOW when the READ or WRITE command is issued, then normal Read or Write
burst operation is executed and the bank remains active at the completion of the burst sequence. If
A10 is HIGH when the Read or Write command is issued, then the Auto-precharge function is
engaged. During Auto-precharge, a Read command will execute as normal with the exception that the
相关PDF资料 |
PDF描述 |
|---|---|
| W972GG8JB-18 | 256M X 8 DDR DRAM, 0.35 ns, PBGA60 |
| W9751G6JB-18 | 32M X 16 DDR DRAM, 0.35 ns, PBGA84 |
| W981204AH-8H | 32M X 4 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| W981216BH75L | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W972GG8JB-3 | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR2 SDRAM 2G-Bit 256Mx8 1.8V 60-Pin WBGA 制造商:Winbond Electronics Corp 功能描述:IC DDR2 SDRAM 2GBIT 3NS |
| W9751G6IB-25 | 功能描述:IC DDR2-800 SDRAM 512MB 84-WBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:2.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.173"，4.40mm 宽） 供应商设备封装:8-MFP 包装:带卷 (TR) |
| W9751G6JB | 制造商:WINBOND 制造商全称:Winbond 功能描述:8M ? 4 BANKS ? 16 BIT DDR2 SDRAM |
| W9751G6JB-25 | 制造商:Winbond Electronics Corp 功能描述:512GB DDRII |
| W9751G6JB-3 | 制造商:Winbond Electronics Corp 功能描述:512MB DDRII |
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