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| 型号： | W972GG8JB-25I |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | DRAM |
| 英文描述： | 256M X 8 DDR DRAM, 0.4 ns, PBGA60 |
| 封装： | 11 X 11.50 MM, ROHS COMPLIANT, WBGA-60 |
| 文件页数： | 8/86页 |
| 文件大小： | 1466K |
| 代理商： | W972GG8JB-25I |
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W972GG8JB
Publication Release Date: Feb. 18, 2011
- 16 -
Revision A02
7.2.3.1
Extended Mode Register for OCD Impedance Adjustment
OCD impedance adjustment can be done using the following EMRS mode. In drive mode all outputs
are driven out by DDR2 SDRAM and drive of RDQS is dependent on EMR bit enabling RDQS
operation. In Drive (1) mode, all DQ, DQS (and RDQS) signals are driven HIGH and all DQS signals
are driven LOW. In Drive (0) mode, all DQ, DQS (and RDQS) signals are driven LOW and all DQS
signals are driven HIGH. In adjust mode, BL = 4 of operation code data must be used. In case of OCD
calibration default, output driver characteristics have a nominal impedance value of 18
Ω during
nominal temperature and voltage conditions. OCD applies only to normal full strength output drive
setting defined by EMR (1) and if reduced strength is set, OCD default driver characteristics are not
applicable. When OCD calibration adjust mode is used, OCD default output driver characteristics are
not applicable. After OCD calibration is completed or driver strength is set to default, subsequent
EMRS commands not intended to adjust OCD chara
cteristics must specify A[9:7] as 000 in order to
maintain the default or calibrated value.
Table 1
– OCD Drive Mode Program
A9
A8
A7
Operation
0
OCD calibration mode exit
0
1
Drive (1) DQ, DQS, (RDQS) HIGH and DQS LOW
0
1
0
Drive (0) DQ, DQS, (RDQS) LOW and
DQS HIGH
1
0
Adjust mode
1
OCD calibration default
7.2.3.2
OCD Impedance Adjust
To adjust output driver impedance, controllers must issue the ADJUST EMRS command along with a
4 bit burst code to DDR2 SDRAM as in table 2. For this operation, Burst Length has to be set to BL =
4 via MRS command before activating OCD and controllers must drive the burst code to all DQs at the
same time. DT0 in table 2 means all DQ bits at bit time 0, DT1 at bit time 1, and so forth. The driver
output impedance is adjusted for all DDR2 SDRAM DQs simultaneously and after OCD calibration, all
DQs and DQSs of a given DDR2 SDRAM will be adjusted to the same driver strength setting. The
maximum step count for adjustment is 16 and when the limit is reached, further increment or
decrement code has no effect. The default setting may be any step within the 16 step range. When
Adjust mode command is issued, AL from previously set value must be applied.
Table 2
– OCD Adjust Mode Program
4 bit burst code inputs to all DQs
Operation
DT0
DT1
DT2
DT3
Pull-up driver strength
Pull-down driver strength
0
NOP (No operation)
0
1
Increase by 1 step
NOP
0
1
0
Decrease by 1 step
NOP
0
1
0
NOP
Increase by 1 step
1
0
NOP
Decrease by 1 step
0
1
0
1
Increase by 1 step
0
1
0
Decrease by 1 step
Increase by 1 step
1
0
1
Increase by 1 step
Decrease by 1 step
1
0
1
0
Decrease by 1 step
Other Combinations
Reserved
相关PDF资料 |
PDF描述 |
|---|---|
| W972GG8JB-18 | 256M X 8 DDR DRAM, 0.35 ns, PBGA60 |
| W9751G6JB-18 | 32M X 16 DDR DRAM, 0.35 ns, PBGA84 |
| W981204AH-8H | 32M X 4 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| W981216BH75L | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| W981216BH-75 | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W972GG8JB-3 | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR2 SDRAM 2G-Bit 256Mx8 1.8V 60-Pin WBGA 制造商:Winbond Electronics Corp 功能描述:IC DDR2 SDRAM 2GBIT 3NS |
| W9751G6IB-25 | 功能描述:IC DDR2-800 SDRAM 512MB 84-WBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:2.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.173"，4.40mm 宽） 供应商设备封装:8-MFP 包装:带卷 (TR) |
| W9751G6JB | 制造商:WINBOND 制造商全称:Winbond 功能描述:8M ? 4 BANKS ? 16 BIT DDR2 SDRAM |
| W9751G6JB-25 | 制造商:Winbond Electronics Corp 功能描述:512GB DDRII |
| W9751G6JB-3 | 制造商:Winbond Electronics Corp 功能描述:512MB DDRII |
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