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参数资料
| 型号： | W989D6CBGX7E |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, 5.4 ns, PBGA54 |
| 封装： | 8 X 9 MM, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, VFBGA-54 |
| 文件页数： | 13/67页 |
| 文件大小： | 1469K |
| 代理商： | W989D6CBGX7E |
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W989D6CB / W989D2CB
512Mb Mobile LPSDR
Publication Release Date: Jun, 27, 2011
- 20 -
Revision A01-004
7.1.12 Mode Register Set Command
(
RAS = L, CAS = L,
WE = L, BA0, BA1, A0~An = Register Data)
The Mode Register Set command is used to program the values of
CAS latency, Addressing Mode and Burst Length in the Mode
Register. The default values in the Mode Register after power-up are undefined; therefore this command must be issued during the
power-up sequence and re-issued after the Deep Power Down Exit Command. Also, this command can be issued while all banks are
in the idle state.
7.1.13 No-Operation Command
(
RAS = H, CAS = H,
WE = H)
The No-Operation command is used in cases such as preventing the device from registering unintended commands. The device
performs no operation when this command is registered. This command is functionally equivalent to the Device Deselect command.
7.1.14 Burst Stop Command
(
RAS = H, CAS = H,
WE = L)
The Burst stop command is used to stop the already activated burst operation. The activated page is left unclosed and future
commands can be issued to access the same page of the active bank. If this command is issued during a burst read operation, the
read data will go to a Hi-Z state after a delay equal to the
CAS latency. If a burst stop command is issued during a burst write
operation, then the burst data is terminated and data bus goes to Hi-Z at the same clock that the burst command is activated. Any
remaining data from the burst write cycle is ignored.
7.1.15 Device Deselect Command
(
CS = H)
The Device Deselect command disables the command decoder so that the
RAS , CAS ,
WE and Address inputs are ignored.
This command is similar to the No-Operation command.
7.1.16 Auto Refresh Command
(
RAS = L, CAS = L,
WE = H, CKE = H, BA0, BA1, A0~An = Don’t care)
The Auto Refresh command is used to refresh the row address provided by the internal refresh counter. The Refresh operation must
be performed 8192 times within 64 ms. The next command can be issued after tRC from the end of the Auto Refresh command.
When the Auto Refresh command is issued, All banks must be in the idle state. The Auto Refresh operation is equivalent to the
CAS -before- RAS operation in a conventional DRAM.
7.1.17 Self Refresh Entry Command
(
RAS = L, CAS = L,
WE = H, CKE = L, BA0, BA1, A0~An = Don’t care)
When the Self Refresh Entry command is issued, the device enters the Self Refresh mode. While the device is in Self Refresh mode,
the device automatically refreshes memory cells, and all input and I/O buffers (except the CKE buffer) are disabled. By asserting the
CKE signal “high” (and by issuing the Self Refresh Exit command), the device exits the Self Refresh mode.
7.1.18 Self Refresh Exit Command
(CKE = H,
CS = H or CKE = H, RAS = H, CAS = H)
This command is issued to exit out of the Self Refresh mode. One tRC delay is required prior to issuing any subsequent command
from the end of the Self Refresh Exit command.
7.1.19 Clock Suspend Mode Entry/Power Down Mode Entry Command
(CKE = L)
The int
ernal CLK is suspended for one cycle when this command is issued (when CKE is asserted “low”). The device state is held
intact while the CLK is suspended. On the other hand, when the device is not operating the Burst cycle, this command performs
entry into Power Down mode. All input and output buffers (except the CKE buffer) are turned off in Power Down mode.
7.1.20 Clock Suspend Mode Exit / Power Down Mode Exit Command
(CKE = H)
When the internal CLK has been suspended, operation of the internal CLK is resumed by providing this command (asserting CKE
“high”). When the device is in Power Down mode, the device exits this mode and all disabled buffers are turned on to the active
state. Any subsequent commands can be issued after one clock cycle from the end of this command.
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相关代理商/技术参数 |
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|---|---|
| W989D6CBGX7G | 制造商:WINBOND 制造商全称:Winbond 功能描述:512Mb Mobile LPSDR |
| W989D6KBGX7E | 制造商:Winbond Electronics Corp 功能描述:IC LPSDR SDRAM 512MBIT 54VFBGA |
| W98AD2KBJX6E | 制造商:Winbond Electronics Corp 功能描述:IC MEMORY SDRAM 1GB 90VFBGA |
| W98AD2KBJX6I | 制造商:Winbond Electronics Corp 功能描述:IC MEMORY SDRAM 1GB 90VFBGA |
| W98M9640 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Semiconductor Discrete Device, P-Channel Power MOS Field Effect Transistor |
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