XR16C2852IJTR-F (Exar) PDF资料下载 Datasheet(4/51 页)

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参数资料

XR16C2852

2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS

REV. 2.1.1

2.11.1

Transmit Holding Register (THR) - Write Only

The transmit holding register is an 8-bit register providing a data interface to the host processor. The host

writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,

parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input

operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data

location.

2.11.2

Transmitter Operation in non-FIFO Mode

The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the

data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled

by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.

2.11.3

Transmitter Operation in FIFO Mode

The host may fill the transmit FIFO with up to 128 bytes of transmit data. The THR empty flag (LSR bit-5) is set

whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the

amount of data in the FIFO falls below its programmed trigger level. The transmit empty interrupt is enabled by

IER bit-1. The TSR flag (LSR bit-6) is set when TSR/FIFO becomes empty.

FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE

Transmit

Holding

(THR)

Transmit Shift Register (TSR)

Data

Byte

THR Interrupt (ISR bit-1)

Enabled by IER bit-1

TXNOFIFO1

16X

Clock

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