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参数资料
| 型号： | XR16C2852IJTR-F |
| 厂商： | Exar Corporation |
| 文件页数： | 50/51页 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 128B 44PLCC |
| 标准包装： | 500 |
| 特点： | * |
| 通道数： | 2，DUART |
| FIFO's： | 128 字节 |
| 规程： | RS232，RS485 |
| 电源电压： | 2.97 V ~ 5.5 V |
| 带自动流量控制功能： | 是 |
| 带IrDA 编码器/解码器： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-LCC（J 形引线） |
| 供应商设备封装： | 44-PLCC（16.59x16.59） |
| 包装： | 带卷 (TR) |
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XR16C2852
xr
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
REV. 2.1.1
8
2.5
Channel A and B Internal Registers
Each UART channel in the 2852 has a set of enhanced registers for control, monitoring and data loading and
unloading. The configuration register set is compatible to those already available in the standard single
16C550 and dual ST16C2550. These registers function as data holding registers (THR/RHR), interrupt status
and control registers (ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/
LCR), modem status and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/
DLM), and a user accessible scratchpad register (SPR).
Beyond the general 16C2550 features and capabilities, the 2852 offers enhanced feature registers (AFR,
EMSR, FLVL, EFR, Xon/Xoff 1, Xon/Xoff 2, FCTR, TRG, FC) that provide automatic RTS and CTS hardware
flow control, Xon/Xoff software flow control, automatic RS-485 half-duplex direction output enable/disable,
FIFO trigger level control, FIFO level counters, and simultaneous writes to both channels. All the register
functions are discussed in full detail later in “Section 3.0, UART INTERNAL REGISTERS” on page 21.
2.6
Simultaneous Write to Channel A and B
During a write mode cycle, the setting of Alternate Function Register (AFR) bit-0 to a logic 1 will override the
CHSEL selection and allows a simultaneous write to both UART channel sections. This functional capability
allow the registers in both UART channels to be modified concurrently, saving individual channel initialization
time. Caution should be considered, however, when using this capability. Any in-process serial data transfer
may be disrupted by changing an active channel’s mode.
2.7
DMA Mode
The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn’t
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# A/B (MF# A/B becomes RXRDY# A/B output when AFR[2:1] = ‘10’) and TXRDY# A/B output
pins. The transmit and receive FIFO trigger levels provide additional flexibility to the user for block mode
operation. The LSR bits 5-6 provide an indication when the transmitter is empty or has an empty location(s) for
more data. The user can optionally operate the transmit and receive FIFO in the DMA mode (FCR bit-3=1).
When the transmit and receive FIFO are enabled and the DMA mode is disabled (FCR bit-3 = 0), the 2852 is
placed in single-character mode for data transmit or receive operation. When DMA mode is enabled (FCR bit-
3 = 1), the user takes advantage of block mode operation by loading or unloading the FIFO in a block
sequence determined by the programmed trigger level. In this mode, the 2852 sets the TXRDY# pin when the
transmit FIFO becomes full, and sets the RXRDY# pin when the receive FIFO becomes empty. The following
table shows their behavior. Also see Figures 20 through 25.
TABLE 1: CHANNEL A AND B SELECT
CS#
CHSEL
FUNCTION
1
X
UART de-selected
0
1
Channel A selected
0
Channel B selected
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