参数资料
| 型号： | XRD98L63AIV-F |
| 厂商： | Exar Corporation |
| 文件页数： | 10/41页 |
| 文件大小： | 0K |
| 描述： | IC CCD DIGITIZER 12BIT 48TQFP |
| 标准包装： | 250 |
| 位数： | 12 |
| 通道数： | 1 |
| 电压 - 电源，模拟： | 2.7 V ~ 3.6 V |
| 电压 - 电源，数字： | 2.7 V ~ 3.6 V |
| 封装/外壳： | 48-TQFP |
| 供应商设备封装： | 48-TQFP（7x7） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页当前第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页
XRD98L63
18
Rev.1.01
Figure 9. Direct ADC Input Mode Timing
ANALOG TO DIGITAL CONVERTER (ADC)
The analog-to-digital converter is based on pipeline
architecture with a built in track & hold input stage. The
track & hold and ADC conversion are controlled by the
externally supplied ADCLK.
The polarity of the ADCLK is programmable. If
ADCpol=low, the track & hold circuit tracks the PGA
output while ADCLK is high and holds while ADCLK is
low. If ADCpol=high, the track & hold circuit tracks the
PGA output while ADCLK is low and holds while ADCLK
is high. ADCLK should be a 50% duty cycle clock, and
should be synchronized with SBLK such that ADC
tracking ends at the same time as the CDS sample
black ends. (See Figure 16).
The ADC reference levels, Vcm, CapP & CapN, are
generated from an internal voltage reference. To mini-
mize noise, these pins should have high frequency
bypass capacitors to AGND. The value of these ca-
pacitors will affect the time required for the reference to
charge up and settle after power-down mode.
The ADC output bus, DB[11:0], has 3-state capability
controlled by the OE bit of the Control register and pin
42, OE. The output bus is enabled when both the OE bit
is high and the OE pin is low. The outputs become high
impedance when either the OE bit is low or the OE pin
is high.
Direct ADC Input Mode
The Direct ADC Input mode connects the CCDin &
REFin pins directly to the ADC inputs, by-passing the
CDS & PGA circuits. To enable the Direct ADC Input
mode, use the Serial Interface to program:
ADCin=1 in the Test register,
DOclamp=0 in the Clock register, and
MinClip=0 in the Control register.
In this mode, the PGA outputs are disabled so there is
no contention at the ADC input nodes. For best perfor-
mance, we recommend using fully differential signals
with a common mode level around 1.2V.
Input Signal
REFin-CCDin
ADCLK
Sample N
ADC tracks
Input Signal
DB[11:0]
Sample N+1
Data N-6
Data N-5
t
DL
Data N-7
相关PDF资料 |
PDF描述 |
|---|---|
| XRT71D00IQ-F | IC JITTER ATTENUATOR SGL 32TQFP |
| XRT71D03IV-F | IC JITTER ATTENUATOR 3CH 64TQFP |
| XRT71D04IV | IC JITTER ATTENUATOR 4CH 80TQFP |
| XRT8000IP-F | IC WAN CLOCK E1/E1 DUAL 18PDIP |
| XRT8001IP-F | IC WAN CLOCK E1/E1 DUAL 18PDIP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XRD98L63AIVTR-F | 制造商:Exar Corporation 功能描述:AFE General Purpose 1ADC 12-Bit 3V 48-Pin TQFP T/R 制造商:Exar Corporation 功能描述:XRD98L63AIVTR-F |
| XRD98L63EVAL | 功能描述:数据转换 IC 开发工具 Eval Board for XRD98L63AIV RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V |
| XRD98L63ZEVAL | 功能描述:数据转换 IC 开发工具 Eval Board (Solder) XRD98L63AIV RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V |
| XRDAN27 | 制造商:EXAR 制造商全称:EXAR 功能描述:Compensating for Zero Order Hold Effects |
| XRDAN28 | 制造商:EXAR 制造商全称:EXAR 功能描述:Frequency Response Effects of Overampling and Averaging on A/D Output Data |
发布紧急采购，3分钟左右您将得到回复。