参数资料
| 型号： | XRD98L63AIV-F |
| 厂商： | Exar Corporation |
| 文件页数： | 19/41页 |
| 文件大小： | 0K |
| 描述： | IC CCD DIGITIZER 12BIT 48TQFP |
| 标准包装： | 250 |
| 位数： | 12 |
| 通道数： | 1 |
| 电压 - 电源，模拟： | 2.7 V ~ 3.6 V |
| 电压 - 电源，数字： | 2.7 V ~ 3.6 V |
| 封装/外壳： | 48-TQFP |
| 供应商设备封装： | 48-TQFP（7x7） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页当前第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页
XRD98L63
26
Rev.1.01
Aperture delays
One of the most difficult tasks in designing a digital
camera is optimizing the pixel timing for the CCD, CDS
and ADC. We have included the programmable aper-
ture delay function to help simplify this job.
There are three serial interface registers, SBLKdly,
SPIXdly, and ADCdly, used to program the aperture
delays. Each register is divided into 2 or 3 delay
parameters.
The delays are added to the clock signals after the
polarity control. This means the definition of leading
edge and trailing edge of the external clock signals
(SBLK, SPIX & ADCLK) depends on the polarity
control bit for each clock. For the default case,
SBLKpol=0, SPIXpol=0 & ADCpol=0, the leading edge
is the falling edge and the trailing edge is the rising
edge.
The SBLKdly register is divided into two 3-bit delay
parameters, SBdly[2:0] and SBdly[5:3]. Each can add
from 0 to 7 ns of delay in 1 ns steps.
SBdly[2:0] controls the delay added to the leading
edge of SBLK. This positions the rising edge of the
internal signal
φ1.
SBdly[5:3] controls the delay added to the trailing edge
of SBLK. This positions the falling edge of the internal
signal
φ1.
The SPIXdly register is divided into three 3-bit delay
parameters, SPdly[2:0], SPdly[5:3] and SPdly[8:6].
Each can add from 0 to 7 ns of delay in 1 ns steps.
SPdly[2:0] controls the delay added to the leading
edge of SPIX. This positions the rising edge of the
internal signal
φ2.
SPdly[5:3] controls the delay added to the trailing edge
of SPIX. This positions the falling edge of the internal
signal
φ2.
SPdly[8:6] is only used when SPIXopt=1. It controls
the delay from the trailing edge of SBLK to the rising
edge of the internal signal
φ2. This delay is in addition
to SBdly[5:3], the SBLK trailing edge delay.
The ADCdly register is divided into two 4-bit delay
parameters, ADCdly[3:0] and ADCdly[7:5]. Each can
add from 0 to 7.5 ns of delay in 0.5 ns steps.
ADCdly[3:0] controls the delay added to the leading
edge of ADCLK. This positions the falling edge of the
internal signal
φ4.
ADCdly[7:4] controls the delay added to the trailing
edge of ADCLK. This positions the rising edge of the
internal signal
φ4.
相关PDF资料 |
PDF描述 |
|---|---|
| XRT71D00IQ-F | IC JITTER ATTENUATOR SGL 32TQFP |
| XRT71D03IV-F | IC JITTER ATTENUATOR 3CH 64TQFP |
| XRT71D04IV | IC JITTER ATTENUATOR 4CH 80TQFP |
| XRT8000IP-F | IC WAN CLOCK E1/E1 DUAL 18PDIP |
| XRT8001IP-F | IC WAN CLOCK E1/E1 DUAL 18PDIP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XRD98L63AIVTR-F | 制造商:Exar Corporation 功能描述:AFE General Purpose 1ADC 12-Bit 3V 48-Pin TQFP T/R 制造商:Exar Corporation 功能描述:XRD98L63AIVTR-F |
| XRD98L63EVAL | 功能描述:数据转换 IC 开发工具 Eval Board for XRD98L63AIV RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V |
| XRD98L63ZEVAL | 功能描述:数据转换 IC 开发工具 Eval Board (Solder) XRD98L63AIV RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V |
| XRDAN27 | 制造商:EXAR 制造商全称:EXAR 功能描述:Compensating for Zero Order Hold Effects |
| XRDAN28 | 制造商:EXAR 制造商全称:EXAR 功能描述:Frequency Response Effects of Overampling and Averaging on A/D Output Data |
发布紧急采购，3分钟左右您将得到回复。