参数资料
型号: XRD98L63AIV-F
厂商: Exar Corporation
文件页数: 40/41页
文件大小: 0K
描述: IC CCD DIGITIZER 12BIT 48TQFP
标准包装: 250
位数: 12
通道数: 1
电压 - 电源,模拟: 2.7 V ~ 3.6 V
电压 - 电源,数字: 2.7 V ~ 3.6 V
封装/外壳: 48-TQFP
供应商设备封装: 48-TQFP(7x7)
包装: 托盘
XRD98L63
8
Rev.1.01
SERIAL INTERFACE
The XRD98L63 uses a three wire serial interface
(LOAD, SDI & SCLK) to access the programmable
features and controls of the chip. The serial interface
uses a 16-bit shift register. The first 6 bits shifted in are
the address bits, the next 10 bits are the data bits. The
address bits select which of the internal registers will
receive the 10 data bits.
The interface will only load data from the shift register
into the register array if there are exactly 16 rising edges
of SCLK while LOAD is low. If more or less rising edges
are present, the data is discarded. There is no checking
of the address bits to ensure a valid register is written
to. If the address bits select an undefined register, the
SCLK
SDI
LOAD
Time
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
t1
t2
t16
t15
t
L1
t
L2
t
SCLK
t
set
t
hold
MSB
LSB
D8
D9
A5
A4
data will be discarded. There is a readback function
(see the Serial Interface Read Back section) that
outputs the contents of a selected register on pins
DB[11:2] of the digital output bus.
The following is the procedure for writing to the serial
interface:
1)
Force LOAD pin low to enable shift register.
2)
Shift in 16 bits, 6 address bits (msb first),
followed by 10 data bits (msb first).
3)
Force LOAD pin high to transfer data from the
shift register to the serial interface register array.
Note: There must be exactly 16 rising edges of
SCLK while LOAD is low.
Figure 4. Serial Interface Timing Diagram
Register Array
SD I
SCLK
LOAD
Register
Select
Da ta Input
Address
Decoder
Address Bits
Da ta Bits
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
MSB
LSB
A4
A5
D8
D9
Read Back
Output Bus
to DB[11:2]
Figure 5. Serial Interface Block Diagram
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