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| 型号： | ZL2106EVAL1Z |
| 厂商： | Intersil |
| 文件页数： | 12/29页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL STEP-DOWN ZL2106 |
| 标准包装： | 1 |
| 系列： | Zilker Labs™ |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 1，非隔离 |
| 输出电压： | 3.3V |
| 电流 - 输出： | 6A |
| 输入电压： | 12V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 400kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ZL2106 |
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ZL2106
from the VDDS pin and supplies bias current internally. A
4.7μF filter capacitor is required at the VRA pin.
Logic
high
ZL
ZL
V IN
V IN
V IN
VDDS
VDDS
VDDS
Open
Multi- mode Pin
Multi- mode Pin
R SET
VR
VR
VR
Logic
low
Pinstrap
Settings
Resistor
Settings
VRA
VRA
VRA
FIGURE 13. PIN-STRAP AND RESISTOR SETTING EXAMPLES
4.5V ≤ V IN ≤ 5.5V
5.5V < V IN ≤ 7.5V
7.5V < V IN ≤ 14V
RESISTOR SETTINGS
This method allows a greater range of adjustability when
connecting a finite value resistor (in a specified range) between
the multi-mode pin and SGND.
Standard 1% resistor values are used, and only every fourth E96
resistor value is used so the device can reliably recognize the
value of resistance connected to the pin while eliminating the
error associated with the resistor accuracy. Up to 31 unique
selections are available using a single resistor.
I 2 C/SMBUS METHOD
ZL2106 functions can be configured via the I 2 C/SMBus interface
using standard PMBus commands. Additionally, any value that
has been configured using the pin-strap or resistor setting
methods can also be re-configured and/or verified via the
I 2 C/SMBus. See Application Note AN2033 for more details.
The SMBus device address and VOUT_MAX are the only
parameters that must be set by external pins. All other device
parameters can be set via the I 2 C/SMBus. The device address is
set using the SA pin. VOUT_MAX is determined as 10% greater
than the voltage set by the VSET pin.
Resistor pin-straps are recommended to be used for all available
device parameters to allow a safe initial power-up before
configuration is stored via the I 2 C/SMBus. For example, this can
be accomplished by pin-strapping the undervoltage lockout
threshold (using SS pin) to a value greater than the expected
input voltage, thus preventing the device from enabling prior to
loading a configuration file.
Power Conversion Functional
Description
Internal Bias Regulators and Input Supply
Connections
The ZL2106 employs three internal low dropout (LDO) regulators
to supply bias voltages for internal circuitry, allowing it to operate
from a single input supply. The internal bias regulators are as
FIGURE 14. INPUT SUPPLY CONNECTIONS
? V2P5: The V2P5 LDO provides a regulated 2.5V bias supply for
the main controller circuitry. It is powered from the VRA LDO
and supplies bias current internally. A 10μF filter capacitor is
required at the V2P5 pin.
When the input supply (VDDS) is higher than 7.5V, the VR and
VRA pins should not be connected to any other pins. These pins
should only have a filter capacitor attached. Due to the dropout
voltage associated with the VR and VRA bias regulators, the
VDDS pin must be connected to these pins for designs operating
from a supply below 7.5V. Figure 14 illustrates the required
connections for all cases.
Note: The internal bias regulators, VR and VRA, are not designed
to be outputs for powering other circuitry. Do not attach external
loads to any of these pins. Only the multi-mode pins may be
connected to the V2P5 pin for logic HIGH settings.
High-side Driver Boost Circuit
The gate drive voltage for the high-side MOSFET driver is
generated by a floating bootstrap capacitor, C B (see Figure 10).
When the lower MOSFET (QL) is turned on, the SW node is pulled
to ground and the capacitor is charged from the internal VR bias
regulator through diode D B . When QL turns off and the upper
MOSFET (QH) turns on, the SW node is pulled up to VDDP and the
voltage on the bootstrap capacitor is boosted approximately 6.5V
above VDDP to provide the necessary voltage to power the high-
side driver. An internal Schottky diode is used with C B to help
maximize the high-side drive supply voltage.
Output Voltage Selection
The output voltage may be set to any voltage between 0.6V and
5.0V provided that the input voltage is higher than the desired
output voltage by an amount sufficient to prevent the device
from exceeding its maximum duty cycle specification. Using the
pin-strap method, V OUT can be set to one of three standard
voltages as shown in Table 2.
TABLE 2. PIN-STRAP OUTPUT VOLTAGE SETTINGS
follows:
? VR: The VR LDO provides a regulated 7V bias supply for the
high-side MOSFET driver circuit. It is powered from the VDDS
pin and supplies bias current internally. A 4.7μF filter capacitor
is required at the VR pin. The VDDS pin directly supplies the
low-side MOSFET driver circuit.
? VRA: The VRA LDO provides a regulated 5V bias supply for the
current sense circuit and other analog circuitry. It is powered
12
VSET
LOW
OPEN
HIGH
V OUT
(V)
1.2
1.5
3.3
FN6852.6
February 20, 2013
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