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参数资料
| 型号： | ZL2106EVAL1Z |
| 厂商： | Intersil |
| 文件页数： | 26/29页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL STEP-DOWN ZL2106 |
| 标准包装： | 1 |
| 系列： | Zilker Labs™ |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 1，非隔离 |
| 输出电压： | 3.3V |
| 电流 - 输出： | 6A |
| 输入电压： | 12V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 400kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ZL2106 |
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ZL2106
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
February, 01, 2013
March 31, 2011
December 16, 2010
December 15, 2010
November 30, 2010
July 9, 2010
July 1, 2010
REVISION
FN6852.6
FN6852.5
FN6852.4
FN6852.3
26
CHANGE
Removed obsolete parts, parts no longer scheduled for release and evaluation board from Ordering Information
table.
Updated Theta JC in Thermal Information from 1 to 1.7.
In “Absolute Maximum Ratings” on page 6, changed following from:
High-Side Supply Voltage for BST Pin . . . . . . . . . . . . . . . . . . . . . -0.3V to 30V
to:
High-Side Supply Voltage for BST Pin . . . . . . . . . . . . . . . . . . . . . -0.3V to 25V
ZL2106ALCF-01
ZL2106ALCFT-01
ZL2106ALCFTK-01
ZL2106ALCF
ZL2106ALCFT
ZL2106ALCFTK
Added corresponding Pb-free lead finish note (Note 2)
In “Voltage Margining” on page 22, changed the last sentence in the 2nd paragraph from "A safety feature prevents the
user from configuring the output voltage to exceed VNOM + 10% under any conditions." to "The ZL2106-01 allows 150%
margin limits."
Updated over temp note in MIN MAX columns of spec table from "Parameters with MIN and/or MAX limits are
100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not
production tested." to new standard "Compliance to datasheet limits is assured by one or more methods:
production test, characterization and/or design."
Removed Note "Limits established by characterization and are not production tested." and all references to it.
Added following statement to disclaimer on page 31: “This product is subject to a license from Power One, Inc.
related to digital power technology as set forth in U.S. Patent No. 7,000,125 and other related patents owned by
Power One, Inc. These license rights do not extend to stand-alone POL regulators unless a royalty is paid to Power
One, Inc.”
Text above Equation 13 changed
From: The reference device must be configured to have a minimum Time-On Delay of 10ms greater than the
member device as shown in Equation 13.
To: The reference device must be configured to have a minimum Time-On Delay and Time-On Rise as shown in
Equation 13.
Made correction to Equation 13 to read
From: tONDLY(REF) >/- tONRISE(REF) + 5ms
To: tON DLY(REF) ≥ tON DLY(MEM) + tON RISE(REF) + 5ms ≥ tON DLY(MEM) + 10ms
Figure 22, last row changed
From: 1.8 5 5 15 5
To: 0.8 5 5 15 5
Revamped Voltage Tracking Section adding details about the tracking feature. Changed in Page 1, 1st paragraph
"The ZL2106 is an innovative power conversion..." to "The ZL2106 is a digital power conversion..."
Made correction to Figure 19 - Connected SDA and SCL to Member device.
Made correction to Figure 23 by changing SDA and SCL labels in each device to “EN”. Added word “Enable” and
added labels CFG, SS, R1, R3, R2 and R4.
Changed in Voltage Tracking - Ratiometric on page 23 first sentence changed from:
“This mode configures the ZL2106 to ramp its output voltage at a rate that is a percentage of the voltage applied
to the VTRK pin”. to “This mode configures the ZL2106 to ramp its output voltage as a percentage of the voltage
applied to the VTRK pin”.
Titles of Table in Figure 22 changed from “Tracking Configuration Example 1A, 1B, 2A, 2B” to “Tracking
Configuration Figure 20 (A), 20 (B), 21 (A), 21 (B)”.
Figures 20and 21 added “0” and “EN” to Timing Tracking Graphics.
FN6852.6
February 20, 2013
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