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参数资料
| 型号： | ZL2106EVAL1Z |
| 厂商： | Intersil |
| 文件页数： | 27/29页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL STEP-DOWN ZL2106 |
| 标准包装： | 1 |
| 系列： | Zilker Labs™ |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 1，非隔离 |
| 输出电压： | 3.3V |
| 电流 - 输出： | 6A |
| 输入电压： | 12V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 400kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ZL2106 |
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ZL2106
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev. (Continued)
DATE
February 11, 2010
November 20, 2009
October 13, 2009
October 1, 2009
REVISION
FN6852.2
FN6852.1
27
CHANGE
Typo on Page 24, Table 15, resistor values 34.8 and 31.6 swapped so that 31.6 is 0x2C and 34.8 is 0x2D in the
table.
On page 16. Table 9. “RSYNC RESISTOR VALUES”. Changed values of last 4 rows from:
34.8kohm | 727kHz
38.3kohm | 800kHz
46.4kohm | 889kHz
51.1kohm | 1000kHz
to:
34.8kohm | 667kHz
38.3kohm | 727kHz
42.2kohm | 889kHz
46.4kohm | 1000kHz
Removed “SNAPSHOT PARAMETERS” table. Added “See AN2033 for details on using Snapshot in addition to the
1) Updated to new format. Updates include:
a) Moving Typical Application Circuits to front of datasheet, per new standard
b) Putting Abs Max, Recommended Operating Conditions and Electrical Specs tables into Intersil format
- Adding Pb-free reflow link to Thermal info
- Adding Intersil's caution statement, per legal
- Added ESD ratings
c) Put Ordering Info table into Intersil format
- Adding Moisture Sensitivity Level note, TB347 tape and reel spec note and Pb-free note (corresponding
to lead finish). Added evaluation board.
d) Updated sales disclaimer on last page to Intersil's verbiage
e) Replaced Zilker POD with Intersil equivalent POD (L36.6x6A)
f) Updated graphics to Intersil standards (font change)
g) Updated cross references to tables (since table #s were removed from Electrical Specs, Abs Max,
Recommended Operating Conditions and Pin Descriptions tables)
h) Updated cross references to figures (since figure #s were removed from Block Diagram and Pinout)
i) Added equation #s to all equations
j) Added Intersil standard over temp notes to Electrical Specs table as follows:
- Added Note 18: "Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise
specified. Temperature limits established by characterization and are not production tested." to MIN MAX columns
of Electrical Specs table.
-Added "Boldface limits apply over the operating temperature range, -40°C to +85°C" to common conditions
of Electrical Specs table. Bolded all MIN and MAX specs in table.
k) Revised page 1. Shortened Features and added Efficiency curve
2) On page 6; Removed "low" from the “Power-good V OUT Low Threshold” line in the Electrical Specs table
3) On page 14; “SOFT-START DELAY AND RAMP SETTINGS” table (was Table 9, now Table 5): Changed UVLO from
4.5V to 7.5V
4) On page 14; “DELAY AND RAMP CONFIGURATION” table (was Table 10, now Table 6): Ramp Time and Delay
Time swapped columns and values changed. Updated UVLO values.
5) On page 10; 2nd column, removed 2nd paragraph "Application notes and reference .. .. to order an evaluation
kit."
6) On page 22; Table 13, “TRACKING MODE CONFIGURATION”, changed UVLO values "4.5" to "5.5" and "10.8" to
"7.5"
7) On page 22; Table 13, “TRACKING MODE CONFIGURATION”, changed Rss values from:
"42.2" to "56.2"
"46.4" to "61.9"
"51.1" to "68.1"
"56.2" to "75"
"61.9" to "82.5"
"68.1" to "90.9"
"75" to "100"
"82.5" to "110
FN6852.6
February 20, 2013
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