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参数资料
| 型号： | ZL2106EVAL1Z |
| 厂商： | Intersil |
| 文件页数： | 4/29页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL STEP-DOWN ZL2106 |
| 标准包装： | 1 |
| 系列： | Zilker Labs™ |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 1，非隔离 |
| 输出电压： | 3.3V |
| 电流 - 输出： | 6A |
| 输入电压： | 12V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 400kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ZL2106 |
第1页第2页第3页当前第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页
ZL2106
Pin Configuration
ZL2106
(36 LD QFN)
TOP VIEW
PG
DGND
SYNC
1
2
3
27
26
25
VDDP
BST
SW
VSET
SA
SCL
SDA
SALRT
FC
4
5
6
7
8
9
ZL2106
Exposed Paddle
Connect to SGND
24
23
22
21
20
19
SW
SW
SW
SW
SW
PGND
FIGURE 4.
Pin Descriptions
TYPE
PIN
1
LABEL
PG
(Note 1)
O
DESCRIPTION
Power-good. This pin transitions high 100ms after output voltage stabilizes within regulation band.
Selectable open drain or push-pull output. Factory default is open drain.
2
3
4
5
6
7
8
9
10
11
12
13
14
15, 16, 17,
DGND
SYNC
VSET
SA
SCL
SDA
SALRT
FC
CFG
SS
VTRK
VSEN
SGND
PGND
PWR
I/O, M
(Note 2)
I, M
I, M
I/O
I/O
O
I, M
I, M
I, M
I
I
PWR
PWR
Digital ground. Common return for digital signals. Connect to low impedance ground plane.
Clock synchronization pin. Used to set switching frequency of internal clock or for synchronization to
external frequency reference.
Output voltage select pin. Used to set V OUT set-point and V OUT max.
Serial address select pin. Used to assign unique SMBus address to each IC.
Serial clock. Connect to external host interface.
Serial data. Connect to external host interface.
Serial alert. Connect to external host interface if desired.
Loop compensation select pin. Used to set loop compensation.
Configuration pin. Used to control the SYNC pin, sequencing and enable tracking.
Soft-start pin. Used to set the ramp delay and ramp time, sets UVLO and configure tracking.
Track sense pin. Used to track an external voltage source.
Output voltage positive feedback sensing pin.
Common return for analog signals. Connect to low impedance ground plane.
Power ground. Common return for internal switching MOSFETs. Connect to low impedance ground plane.
18, 19
20, 21, 22,
SW
I/O
Switching node (level-shift common).
23, 24, 25
26
27, 28, 29
30
BST
VDDP
VDDS
PWR
PWR
PWR
4
Bootstrap voltage for level-shift driver (referenced to SW).
Bias supply voltage for internal switching MOSFETs (return is PGND).
IC supply voltage (return is SGND).
FN6852.6
February 20, 2013
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