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| 型号： | ZL2106EVAL1Z |
| 厂商： | Intersil |
| 文件页数： | 15/29页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL STEP-DOWN ZL2106 |
| 标准包装： | 1 |
| 系列： | Zilker Labs™ |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 1，非隔离 |
| 输出电压： | 3.3V |
| 电流 - 输出： | 6A |
| 输入电压： | 12V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 400kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ZL2106 |
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ZL2106
Power-good (PG)
The ZL2106 provides a Power-good (PG) signal that indicates the
output voltage is within a specified tolerance of its target level
and no fault condition exists. By default, the PG pin will assert if
the output is within +15%/-10% of the target voltage. These
limits may be changed via the I 2 C/SMBus interface. See
Application Note AN2033 for details.
A PG delay period is the time from when all conditions for
asserting PG are met and when the PG pin is actually asserted.
This feature is commonly used instead of an external reset
controller to signal the power supply is at its target voltage prior
to enabling any powered circuitry. By default, the ZL2106 PG
delay is set to 1ms and may be changed using the I 2 C/SMBus
interface as described in AN2033.
Switching Frequency and PLL
The ZL2106 incorporates an internal phase-locked loop (PLL) to
clock the internal circuitry. The PLL can be driven by an external
clock source connected to the SYNC pin. When using the internal
oscillator, the SYNC pin can be configured as a clock source for
other Zilker Labs devices.
The SYNC pin is a unique pin that can perform multiple functions
depending on how it is configured. The CFG pin is used to select
the operating mode of the SYNC pin as shown in Table 4. Figure
16 illustrates the typical connections for each mode.
TABLE 7. SYNC PIN FUNCTION SELECTION
CONFIGURATION A: SYNC OUTPUT
When the SYNC pin is configured as an output (CFG pin is tied HIGH),
the device will run from its internal oscillator and will drive the
resulting internal oscillator signal (preset to 400kHz) onto the SYNC
pin so other devices can be synchronized to it. The SYNC pin will not
be checked for an incoming clock signal while in this mode.
CONFIGURATION B: SYNC INPUT
When the SYNC pin is configured as an input (CFG pin is tied
LOW), the device will automatically check for an external clock
signal on the SYNC pin each time the EN pin is asserted. The
internal oscillator will then synchronize with the rising edge of the
external clock. The incoming clock signal must be in the range of
200kHz to 1MHz with a minimum duty cycle and must be stable
when the EN pin is asserted. The external clock signal must also
exhibit the necessary performance requirements (see the
“Electrical Specifications” table beginning on page 6).
In the event of a loss of the external clock signal, the output
voltage may show transient over/undershoot. If this happens, the
ZL2106 will automatically switch to its internal oscillator and
switch at a frequency close to the previous incoming frequency.
CONFIGURATION C: SYNC AUTO DETECT
When the SYNC pin is configured in auto detect mode (CFG pin is left
OPEN), the device will automatically check for a clock signal on the
SYNC pin after enable is asserted. If a valid clock signal is present,
the ZL2106’s oscillator will then synchronize with the rising edge of
the external clock (refer to SYNC INPUT description).
CFG PIN
LOW
OPEN
HIGH
SYNC PIN FUNCTION
SYNC is configured as an input
Auto detect mode
SYNC is configured as an output f SW = 400kHz
Logic
high
SYNC
If no incoming clock signal is present, the ZL2106 will configure
the switching frequency according to the state of the SYNC pin as
listed in Table 8. In this mode, the ZL2106 will only read the
SYNC pin connection during the start-up sequence. Changes to
the SYNC pin connection will not affect f SW until the power
(VDDS) is cycled off and on again.
SYNC
200kHz – 1MHz
N/C
ZL2106
A) SYNC = output
Logic
200kHz – 1MHz
N/C
ZL2106
B) SYNC = input
N/C
high
SYNC
Open
SYNC
SYNC
200kHz – 1MHz
ZL2106
OR
Logic
ZL2106
OR
R SYNC
ZL2106
low
C) SYNC = Auto Detect
FIGURE 16. SYNC PIN CONFIGURATIONS
15
FN6852.6
February 20, 2013
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