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参数资料
| 型号： | ZL2106EVAL1Z |
| 厂商： | Intersil |
| 文件页数： | 7/29页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL STEP-DOWN ZL2106 |
| 标准包装： | 1 |
| 系列： | Zilker Labs™ |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 1，非隔离 |
| 输出电压： | 3.3V |
| 电流 - 输出： | 6A |
| 输入电压： | 12V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 400kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ZL2106 |
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ZL2106
Electrical Specifications V DDP = V DDS = 12V, T A = -40°C to +85°C unless otherwise noted. (Note 8) Typical values are at T A = +25°C.
Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
MIN
MAX
PARAMETER
Soft-start Delay Duration Accuracy
CONDITIONS
Turn-on delay (precise mode)
(Note 18)
TYP
±0.25
(Note 18)
UNIT
ms
(Notes 11, 12)
Turn-on delay (normal mode) (Note 13)
Turn-off delay (Note 13)
-0.25/+4
-0.25/+4
ms
ms
Soft-start Ramp Duration Range
Set using SS pin or resistor
2
20
ms
Soft-start Ramp Duration Accuracy
Set using
I 2 C/SMBus
0
100
200
ms
μs
Logic Input/Output Characteristics
Logic Input Leakage Current
Logic input low, V IL
Logic input OPEN (N/C)
Logic Input High, V IH
Digital pins
Multi-mode logic pins
-250
2.0
1.4
250
0.8
nA
V
V
V
Logic Output Low, V OL
Logic Output High, V OH
I OL ≤ 4mA
I OH ≥ -2mA
2.25
0.4
V
V
Oscillator and Switching Characteristics
Switch Node Current, I SW
Switching Frequency Range
Peak (source or sink) (Note 14)
200
9
1000
A
kHz
Switching Frequency Set-point Accuracy
PWM Duty Cycle (Max)
Predefined settings (Table 9)
Factory default (Note 15)
-5
5
95
%
%
(Note 16)
SYNC Pulse Width (Min)
150
ns
Input Clock Frequency Drift Tolerance
r DS(ON) of High Side N-channel FETs
r DS(ON) of Low Side N-channel FETs
External clock source
I SW = 6A, V GS = 6.5V
I SW = 6A, V GS = 12V
-13
60
43
13
85
65
%
m Ω
m Ω
Tracking
VTRK Input Bias Current
VTRK Tracking Ramp Accuracy
VTRK Regulation Accuracy
VTRK = 5.5V
100% Tracking, V OUT - VTRK
100% Tracking, V OUT - VTRK
-100
-1
110
200
100
1
μA
mV
%
Fault Protection Characteristics
UVLO Threshold Range
Configurable via I 2 C/SMBus
2.85
16
V
UVLO Set-point Accuracy
UVLO Hysteresis
Factory default
-150
3
150
mV
%
UVLO Delay
Power-good V OUT Threshold
Power-good V OUT Hysteresis
Configurable via
Factory default
Factory default
I 2 C/SMBus
0
90
5
100
2.5
%
μs
% V OUT
%
Power-good Delay
Using pin-strap or resistor
2
20
ms
Configurable via
I 2 C/SMBus
0
500
s
7
FN6852.6
February 20, 2013
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