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| 型号： | A42MX24-3VQ100A |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件页数： | 24/93页 |
| 文件大小： | 854K |
| 代理商： | A42MX24-3VQ100A |
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30
Data Device Corporation
www.ddc-web.com
BU-6474X/6484X/6486X
J-07/05-0
RT DESCRIPTOR STACK
The descriptor stack provides a chronology of all messages
processed by the Mini-ACE Mark3 RT. Reference FIGURES 6, 7,
and 8. Similar to BC mode, there is a four-word block descriptor
in the Stack for each message processed. The four entries to
each block descriptor are the Block Status Word, Time Tag Word,
the pointer to the start of the message's data block, and the 16-
bit received Command Word.
The RT Block Status Word includes indications of whether a par-
ticular message is ongoing or has been completed, what bus
channel it was received on, indications of illegal commands, and
flags denoting various message error conditions. For the double
buffering, subaddress circular buffering, and global circular
buffering modes, the data block pointer may be used for locating
the data blocks for specific messages. Note that for mode code
commands, there is an option to store the transmitted or
received data word as the third word of the descriptor, in place of
the data block pointer.
The Time Tag Word provides a 16-bit indication of relative time
for individual messages. The resolution of the Mini-ACE Mark3's
time tag is programmable from among 2, 4, 8, 16, 32, or 64
s/LSB. There is also a provision for using an external clock input
for the time tag. If enabled, there is a time tag rollover interrupt,
which is issued when the value of the time tag rolls over from
FFFF(hex) to 0. Other time tag options include the capabilities to
clear the time tag register following receipt of a Synchronize
(without data) mode command and/or to set the time tag follow-
ing receipt of a Synchronize (with data) mode command. For the
latter, there is an added option to filter the "set" capability based
on the LSB of the received data word being equal to logic "0".
RT INTERRUPTS
The Mini-ACE Mark3 offers a great deal of flexibility in terms of
RT interrupt processing. By means of the Mini-ACE Mark3’s two
Interrupt Mask Registers, the RT may be programmed to issue
interrupt requests for the following events/conditions: End-of-
(every)Message, Message Error, Selected (transmit or receive)
Subaddress, 100% Circular Buffer Rollover, 50% Circular Buffer
Rollover, 100% Descriptor Stack Rollover, 50% Descriptor Stack
Rollover, Selected Mode Code, Transmitter Timeout, Illegal
Command, and Interrupt Status Queue Rollover.
Interrupts for 50% Rollovers of Stacks and Circular Buffers.
The Mini-ACE Mark3 RT and Monitor are capable of issuing host
interrupts when a subaddress circular buffer pointer or stack
pointer crosses its mid-point boundary. For RT circular buffers,
this is applicable for both transmit and receive subaddresses.
Reference FIGURE 9. There are four interrupt mask and inter-
rupt status register bits associated with the 50% rollover
function:
(1) RT circular buffer;
(2) RT command (descriptor) stack;
(3) Monitor command (descriptor) stack; and
(4) Monitor data stack.
The 50% rollover interrupt is beneficial for performing bulk data
transfers. For example, when using circular buffering for a partic-
ular receive subaddress, the 50% rollover interrupt will inform the
host processor when the circular buffer is half full. At that time,
the host may proceed to read the received data words in the
upper half of the buffer, while the Mini-ACE Mark3 RT writes
received data words to the lower half of the circular buffer. Later,
when the RT issues a 100% circular buffer rollover interrupt, the
host can proceed to read the received data from the lower half of
the buffer, while the Mini-ACE Mark3 RT continues to write
received data words to the upper half of the buffer.
Interrupt status queue. The Mini-ACE Mark3 RT, Monitor, and
combined RT/Monitor modes include the capability for generat-
ing an interrupt status queue. As illustrated in FIGURE 10, this
provides a chronological history of interrupt generating events
and conditions. In addition to the Interrupt Mask Register, the
Interrupt Status Queue provides additional filtering capability,
such that only valid messages and/or only invalid messages may
result in the creation of an entry to the Interrupt Status Queue.
Queue entries for invalid and/or valid messages may be disabled
by means of bits 8 and 7 of configuration register #6.
The interrupt status queue is 64 words deep, providing the capa-
bility to store entries for up to 32 messages. These events and
conditions include both message-related and non-message
related events. Note that the Interrupt Vector Queue Pointer
Register will always point to the next location (modulo 64) fol-
lowing the last vector/pointer pair written by the Mini-ACE Mark3
RT.
The pointer to the Interrupt Status Queue is stored in the INTER-
RUPT VECTOR QUEUE POINTER REGISTER (register
address 1F). This register must be initialized by the host, and is
subsequently incremented by the RT message processor. The
interrupt status queue is 64 words deep, providing the capability
to store entries for up to 32 messages.
The queue rolls over at addresses of modulo 64. The events that
result in queue entries include both message-related and non-
message-related events. Note that the Interrupt Vector Queue
Pointer Register will always point to the next location (modulo 64)
following the last vector/pointer pair written by the Mini-ACE
Mark3 RT, Monitor, or RT/Monitor.
Each event that causes an interrupt results in a two-word entry
to be written to the queue. The first word of the entry is the inter-
rupt vector. The vector indicates which interrupt event(s)/condi-
tion(s) caused the interrupt.
The interrupt events are classified into two categories: message
interrupt events and non-message interrupt events. Message-
相关PDF资料 |
PDF描述 |
|---|---|
| A42MX24-3VQ100B | 40MX and 42MX FPGA Families |
| A42MX36-2PQ100B | 40MX and 42MX FPGA Families |
| A42MX36-2PQ100ES | 40MX and 42MX FPGA Families |
| A42MX36-2TQ100 | 40MX and 42MX FPGA Families |
| A42MX36-2TQ100A | 40MX and 42MX FPGA Families |
相关代理商/技术参数 |
参数描述 |
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| A42MX24-FPL84 | 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
| A42MX24-FPLG84 | 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
| A42MX24-FPQ160 | 功能描述:IC FPGA MX SGL CHIP 36K 160-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
| A42MX24-FPQ208 | 功能描述:IC FPGA MX SGL CHIP 36K 160-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
| A42MX24-FPQG160 | 功能描述:IC FPGA MX SGL CHIP 36K 160-PQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
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