参数资料
型号: A42MX24-3VQ100A
厂商: Electronic Theatre Controls, Inc.
英文描述: 40MX and 42MX FPGA Families
中文描述: 40MX和42MX FPGA系列
文件页数: 33/93页
文件大小: 854K
代理商: A42MX24-3VQ100A
39
Data Device Corporation
www.ddc-web.com
BU-6474X/6484X/6486X
J-07/05-0
HOST
CH. A
TX/RXA
CH. B
TX/RXB
RTAD4-RTAD0
RT
ADDRESS,
PARITY
RTADP
D15-D0
+3.3V
CLK IN
CLOCK
OSCILLATOR
N/C
POLARITY_SEL
(NOTE 2)
ZERO_WAIT
(NOTE 3)
ADDRESS
DECODER
SELECT
MEM/REG
RD/WR
STRBD
READYD
TAG_CLK
RD/WR
CPU STROBE
CPU ACKNOWLEDGE
(NOTE 4)
RESET
+3.3 V
MSTCLR
SSFLAG/EXT_TRIG
INT
CPU INTERRUPT REQUEST
NOTES:
1. CPU ADDRESS LATCH SIGNAL PROVIDED BY PROCESSORS WITH MULTIPLEXED ADDRESS/DATA BUSES. FOR PROCESSORS WITH NON-MULTIPLEXED
ADDRESS AND DATA BUSES, ADDR_LAT SHOULD BE CONNECTED TO +3.3V.
2. IF POLARITY_SEL = "1", RD/WR IS HIGH TO READ, LOW TO WRITE. IF POLARITY_SEL = "0", RD/WR IS LOW TO READ, HIGH TO WRITE.
3. ZERO_WAIT SHOULD BE STRAPPED TO LOGIC "1" FOR NON-ZERO WAIT INTERFACE AND TO LOGIC "0" FOR ZERO WAIT INTERFACE.
4. CPU ACKNOWLEDGE PROCESSOR INPUT ONLY FOR NON-ZERO WAIT TYPE OF INTERFACE.
A15-A12
A11-A0
N/C
ADDR_LAT
TRANSPARENT/BUFFERED
CPU ADDRESS LATCH (NOTE 1)
+3.3V
16/8_BIT
TRIGGER_SEL
MSB/LSB
+3.3 V
Mini-ACE
Mark3
+3.3V
FIGURE 12. HOST PROCESSOR INTERFACE - 16-BIT BUFFERED CONFIGURATION
(SHOWN FOR +3.3 VOLTS ONLY)
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