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| 型号： | A42MX24-3VQ100A |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件页数： | 32/93页 |
| 文件大小： | 854K |
| 代理商： | A42MX24-3VQ100A |
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38
Data Device Corporation
www.ddc-web.com
BU-6474X/6484X/6486X
J-07/05-0
accessible by means of the BIT status register. For RT mode, the
result of the self-test may be communicated to the bus controller
via bit 8 of the RT BIT word ("0" = pass, "1" = fail).
Assuming that the protocol self-test passes, all of the register
and shared RAM locations will be restored to their state prior to
the self-test, with the exception of the 60 RAM address locations
0342-037D and the TIME TAG REGISTER. Note that for RT
mode, these locations map to the illegalization lookup table for
"broadcast transmit subaddresses 1 through 30" (non-mode
code subaddresses). Since MIL-STD-1553 does not define
these as valid command words, this section of the illegalization
lookup table is normally not used during RT operation. The TIME
TAG REGISTER will continue to increment during the self-test.
If there is a failure of the protocol self-test, it is possible to access
information about the first failed vector. This may be done by means
of the Mini-ACE Mark3's upper registers (register addresses 32
through 63). Through these registers, it is possible to determine the
self-test ROM address of the first failed vector, the expected
response data pattern (from the ROM), the register or memory
address, and the actual (incorrect) data value read from register or
memory. The on-chip self-test ROM is 4K X 24.
Note that the RAM self-test is destructive. That is, following the
RAM self-test, regardless of whether the test passes or fails, the
shared RAM is not restored to its state prior to this test. Following
a failed RAM self-test, the host may read the internal RAM to
determine which location(s) failed the walking pattern test.
RAM PARITY
The BC/RT/MT version of the Mini-ACE Mark3 is available with
options of 4K or 64K words of internal RAM. For the 64K option,
the RAM is 17 bits wide. The 64K X 17 internal RAM allows for par-
ity generation for RAM write accesses, and parity checking for
RAM read accesses. This includes host RAM accesses, as well as
accesses by the Mini-ACE Mark3’s internal logic. When the Mini-
ACE Mark3 detects a RAM parity error, it reports it to the host
processor by means of an interrupt and a register bit. Also, for the
RT and Selective Message Monitor modes, the RAM address
where a parity error was detected will be stored on the Interrupt
Status Queue (if enabled).
RELOCATABLE MEMORY MANAGEMENT LOCATIONS
In the Mini-ACE Mark3’s default configuration, there is a
fixed
area of shared RAM addresses, 0000h-03FF, that is allocated for
storage of the BC's or RT's pointers, counters, tables, and other
"non-message" data structures. As a means of reducing the over-
all memory address space for using multiple Mini-ACE Mark3’s in
a given system (e.g., for use with the DMA interface configura-
tion), the Mini-ACE Mark3 allows this area of RAM to be relocat-
ed by means of 6 configuration register bits. To provide backwards
compatibility to ACE and Mini-ACE, the default for this RAM area
is 0000h-03FFh.
HOST PROCESSOR INTERFACE
The Mini-ACE Mark3 supports a wide variety of processor inter-
face configurations. These include shared RAM and DMA con-
figurations, straightforward interfacing for 16-bit and 8-bit buses,
support for both non-multiplexed and multiplexed address/data
buses, non-zero wait mode for interfacing to a processor
address/data buses, and zero wait mode for interfacing (for
example) to microcontroller I/O ports. In addition, with respect to
the ACE/Mini-ACE, the Mini-ACE Mark3 provides two major
improvements: (1) reduced maximum host access time for
shared RAM mode; and (2) increased maximum DMA grant time
for the transparent/DMA mode.
The Mini-ACE Mark3's maximum host holdoff time (time prior to
the assertion of the READYD handshake signal) has been sig-
nificantly reduced. For ACE/Mini-ACE, this maximum holdoff
time is 17 internal word transfer cycles, resulting in an overall
holdoff time of approximately 4.6 s, using a 16 MHz clock. By
comparison, using the Mini-ACE Mark3's ENHANCED CPU
ACCESS feature, this worst-case holdoff time is reduced signifi-
cantly, to a single internal transfer cycle. For example, when
operating the Mini-ACE Mark3 in its 16-bit buffered, non-zero
wait configuration with a 16 MHz clock input, this results in a
maximum overall host transfer cycle time of 632 ns for a read
cycle, or 570 ns for a write cycle.
In addition, when using the ACE or Mini-ACE in the transpar-
ent/DMA configuration, the maximum request-to-grant time,
which occurs prior to an RT start-of-message sequence, is
4.0 s with a 16 MHz clock, or 3.5 s with a 12 MHz clock. For
the Mini-ACE Mark3 functioning as a MIL-STD-1553B RT, this
time has been increased to 8.5 s at 10 MHz, 9 s at 12 MHz,
10 s at 16 MHz, and 10.5 s at 20MHz. This provides greater
flexibility, particularly for systems in which a host has to arbitrate
among multiple DMA requestors.
By far, the most commonly used processor interface configura-
tion is the 16-bit buffered, non-zero wait mode. This configuration
may be used to interface between 16-bit or 32-bit microproces-
sors and an Mini-ACE Mark3. In this mode, only the Mini-ACE
Mark3's internal 4K or 64K words of internal RAM are used for
storing 1553 message data and associated "housekeeping"
functions. That is, in this configuration, the Mini-ACE Mark3 will
never attempt to access memory on the host bus.
FIGURE 12 illustrates a generic connection diagram between a 16-
bit (or 32-bit) microprocessor and an Mini-ACE Mark3 for the 16-bit
buffered configuration, while FIGURES 13 and 14, and associated
tables illustrate the processor read and write timing respectively.
相关PDF资料 |
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| A42MX24-3VQ100B | 40MX and 42MX FPGA Families |
| A42MX36-2PQ100B | 40MX and 42MX FPGA Families |
| A42MX36-2PQ100ES | 40MX and 42MX FPGA Families |
| A42MX36-2TQ100 | 40MX and 42MX FPGA Families |
| A42MX36-2TQ100A | 40MX and 42MX FPGA Families |
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