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参数资料
| 型号： | A42MX24-3VQ100A |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件页数： | 51/93页 |
| 文件大小： | 854K |
| 代理商： | A42MX24-3VQ100A |
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55
Data Device Corporation
www.ddc-web.com
BU-6474X/6484X/6486X
J-07/05-0
SLEEPIN (I)
UPADDREN
(I)
For 64K RAM versions with internal transceivers, this signal is always configured as SLEEPIN.
This signal is used to control the transceiver sleep (power-down) circuitry. For these
versions of Mark3 if SLEEPIN is connected to logic "0", the transceivers are fully pow-
ered and operate normally. If SLEEPIN is connected to logic "1", the transceivers are in
sleep mode (dormant, low-power mode) of operation and are NOT operational.
For 4K RAM versions, this signal is always configured as UPADDREN.
This signal is used to control the function of the upper 4 address inputs (A15-A12). For
these versions of Mark3 if UPADDREN is connected to logic "1", then these four signals
operate as address lines A15-A12. If UPADDREN is connected to logic "0", then A15
and A14 function as CLK_SEL_1 and CLK_SEL_0 respectively; A13 MUST be con-
nected to +3.3V-LOGIC; and A12 functions as RTBOOT.
For 64K RAM transceiverless versions, this signal is always a No Connect (NC).
14
INT (O)
Interrupt Request output.
If the LEVEL/PULSE interrupt bit (bit 3) of Configuration Register #2 is logic "0", a neg-
ative pulse of approximately 500ns in width is output on INT to signal an interrupt
request.
If LEVEL/PULSE is high, a low level interrupt request output will be asserted on INT.
The level interrupt will be cleared (high) after either: (1) The processor writes a value of
logic "1" to INTERRUPT RESET, bit 2 of the Start/Reset Register; or (2) If bit 4 of
Configuration Register #2, INTERRUPT STATUS AUTO-CLEAR is logic "1" then it will
only be necessary to read the Interrupt Status Register (#1 and/or #2) that is request-
ing an interrupt enabled by the corresponding Interrupt Mask Register. However, for the
case where both Interrupt Status Register #1 and Interrupt Status Register #2 have bits
set reflecting interrupt events, it will be necessary to read both interrupt status registers
in order to clear INT.
63
CLOCK_IN (I)
20 MHz, 16 MHz, 12 MHz, or 10 MHz clock input.
26
TX_INH_A (I)
Transmitter inhibit inputs for Channel A and Channel B, MIL-STD-1553 transmitters.
For normal operation, these inputs should be connected to logic "0". To force a shut-
down of Channel A and/or Channel B, a value of logic "1" should be applied to the
respective TX_INH input.
65
TX_INH_B (I)
67
Master Clear. Negative true Reset input, normally asserted low following power turn-on.
MSTCLR(I)
25
Time Tag Clock. External clock that may be used to increment the Time Tag Register. This
option is selected by setting Bits 7, 8 and 9 of Configuration Register # 2 to Logic "1".
TAG_CLK (I)
23
INCMD (O) /
MCRST (O)
In-command or Mode Code Reset.
The function of this pin is controlled by bit 0 of Configuration Register #7, MODE CODE
RESET/INCMD SELECT.
If this register bit is logic "0" (default), INCMD will be active on this pin. For BC, RT, or
Selective Message Monitor modes, INCMD is asserted low whenever a message is
being processed by the Mark3. In Word Monitor mode, INCMD will be asserted low for
as long as the monitor is online.
For RT mode, if MODE CODE RESET/INCMD SELECT is programmed to logic "1",
MCRST will be active. In this case, MCRST will be asserted low for two clock cycles fol-
lowing receipt of a Reset remote terminal mode command.
In BC or Monitor modes, if MODE CODE RESET/INCMD SELECT is logic "1", this sig-
nal is inoperative; i.e., in this case, it will always output a value of logic "1".
32
TABLE 55. MISCELLANEOUS
SIGNAL NAME
DESCRIPTION
BU-6474XF/GX
BU-6484XF/GX
BU-64863F/GX
PIN
4K RAM
(BU-6474XF/GX
BU-6484XF/GX)
NC
64K RAM
(BU-64863F/G0)
64K RAM
(BU-64863F/G8
BU-64863F/G9)
FLAT PACK AND GULL WING PACKAGES - SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS (CONT.)
相关PDF资料 |
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|---|---|
| A42MX24-3VQ100B | 40MX and 42MX FPGA Families |
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| A42MX36-2PQ100ES | 40MX and 42MX FPGA Families |
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相关代理商/技术参数 |
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| A42MX24-FPL84 | 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
| A42MX24-FPLG84 | 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
| A42MX24-FPQ160 | 功能描述:IC FPGA MX SGL CHIP 36K 160-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
| A42MX24-FPQ208 | 功能描述:IC FPGA MX SGL CHIP 36K 160-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
| A42MX24-FPQG160 | 功能描述:IC FPGA MX SGL CHIP 36K 160-PQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
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