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| 型号： | A4960KJPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 13/35页 |
| 文件大小： | 0K |
| 描述： | IC BLDC CTLR BRUSHLESS 32LQFP |
| 标准包装： | 1 |
| 系列： | * |
| 应用： | * |
| 输出数： | * |
| 电流 - 输出： | * |
| 电压 - 负载： | * |
| 电源电压： | * |
| 工作温度： | * |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP 裸露焊盘 |
| 供应商设备封装： | 32-LQFP（7x7） |
| 包装： | 标准包装 |
| 其它名称： | 620-1452-6 |
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A4960
Automotive, Sensorless BLDC Controller
Functional Description
The A4960 is a three-phase, sensorless, brushless DC (BLDC)
motor controller for use with external N-channel power
MOSFETs and is specifically designed for automotive applica-
tions. The motor is driven using block commutation (trapezoidal
drive), where phase commutation is determined by a proprietary,
motor back-EMF (BEMF) sensing technique. The motor BEMF
is sensed to determine the rotor position without any requirement
for independent position sensors.
Motor current is provided by six external N-channel power
MOSFETs arranged as a three-phase bridge. The A4960 provides
six high current gate drives, three high-side and three low-side,
capable of driving a wide range of MOSFETs. It includes all the
necessary circuits to ensure that the gate-source voltage of both
high-side and low-side MOSFETs are above 10 V at motor sup-
ply voltages down to 7 V.
An integrated start-up scheme can be configured with program-
mable parameters through a serial interface allowing the A4960
to be adjusted for a wide range of motor and load combinations.
The serial interface also provides the ability to program various
gate drive and diagnostic parameters.
Integrated diagnostics provide indication of undervoltage, over-
temperature, and power bridge faults. They can be configured to
protect the power MOSFETs under most short circuit conditions.
Detailed diagnostic information is available through the serial
interface.
Specific functions are described more fully in following sections.
Input and Output Terminal Functions
VBB Main power supply for internal regulators and charge pump.
The main power supply should be connected to VBB through a
reverse voltage protection circuit and should be decoupled with
ceramic capacitors connected close to the supply and ground
terminals.
VDD Logic supply. Compatible with 3.3 V and 5 V logic. This
should be decoupled to ground with a 100 nF capacitor.
CP1, CP2 Pump capacitor connections for charge pump. Connect
a 220 nF ceramic capacitor between CP1 and CP2.
VREG Regulated voltage, nominally 13 V, used to supply the low
side gate drivers and to charge the bootstrap capacitors. A suffi-
ciently large storage capacitor must be connected to this terminal
to provide the transient charging current.
REF Voltage reference input to internal reference DAC. Connect
to VDD to use the internal 2 V reference.
GND Analog reference, digital and power ground. Connect to
supply ground.
VBRG Sense input to the top of the external MOSFET bridge.
Allows accurate measurement of the voltage at the drain of the
high-side MOSFETs.
CA, CB, CC High-side connections for the bootstrap capacitors
and positive supply for high-side gate drivers.
GHA, GHB, GHC High-side, gate-drive outputs for external
N-channel MOSFETs.
SA, SB, SC Motor phase connections. These terminals sense the
voltages switched across the load. They are also connected to the
negative side of the bootstrap capacitors and are the negative sup-
ply connections for the floating high-side drivers.
GLA, GLB, GLC Low-side, gate-drive outputs for external
N-channel MOSFETs.
LSS Low-side return path for discharge of the capacitance on the
MOSFET gates, connected to the common sources of the low-
side external MOSFETs through a low impedance track.
CSP, CSM Current sense amplifier inputs. Connect directly to
each end of the sense resistor using separate PCB traces.
PWM PWM input to control high-side switching. When pulsed
low, this turns off any active high-side drivers and turns on the
complementary low-side drivers. When held low for longer than
the PWM brake time, this turns off all high-side drivers and turns
on all low-side drivers, when RUN (bit 0 in the Run register) is
set to 1.
RESETN Resets faults when pulsed low. Forces low-power
shutdown (sleep mode) when held low for more than the reset
shutdown width, t RSD ?.?Can?be?pulled?to?VBB?with?22?kΩ?resistor.
SDI Serial data input. 16-bit serial word input, MSB first.
SDO Serial data output. High impedance when STRN is high.
Outputs FF (bit 15 of the Diagnostic register), the Fault flag, as
soon as STRN goes low.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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相关代理商/技术参数 |
参数描述 |
|---|---|
| A4960SJPTR-T | 制造商:Allegro MicroSystems LLC 功能描述: |
| A496-2 | 制造商:APEM 功能描述:Switch Access Push Button Switch Round Cap |
| A4962KLPTR-T | 功能描述:IC MOTOR CONTROLLER 制造商:allegro microsystems, llc 系列:* 零件状态:有效 标准包装:4,000 |
| A496-3 | 制造商:APEM 功能描述: |
| A4963GLPTR-T | 功能描述:Motor Driver Power MOSFET SPI 20-TSSOP-EP 制造商:allegro microsystems, llc 系列:- 包装:剪切带（CT） 零件状态:有效 电机类型 - 步进:- 电机类型 - AC，DC:无刷 DC（BLDC） 功能:控制器 - 换向，方向管理 输出配置:前置驱动器 - 半桥（3） 接口:SPI 技术:功率 MOSFET 步进分辨率:- 应用:通用 电流 - 输出:- 电压 - 电源:4.2 V ~ 50 V 电压 - 负载:- 工作温度:-25°C ~ 150°C（TA） 安装类型:表面贴装 封装/外壳:20-TSSOP（0.173"，4.40mm 宽）裸焊盘 供应商器件封装:20-TSSOP-EP 标准包装:1 |
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