参数资料
型号: A4960KJPTR-T
厂商: Allegro Microsystems Inc
文件页数: 18/35页
文件大小: 0K
描述: IC BLDC CTLR BRUSHLESS 32LQFP
标准包装: 1
系列: *
应用: *
输出数: *
电流 - 输出: *
电压 - 负载: *
电源电压: *
工作温度: *
安装类型: 表面贴装
封装/外壳: 32-LQFP 裸露焊盘
供应商设备封装: 32-LQFP(7x7)
包装: 标准包装
其它名称: 620-1452-6
A4960
Automotive, Sensorless BLDC Controller
Low-side gate drive
The low-side gate drive outputs GLA, GLB, and GLC are refer-
enced to the LSS terminal. These outputs are designed to drive
external N-channel power MOSFETs. External resistors between
each gate drive output and the gate connection to the respective
MOSFET (as close as possible to the MOSFET) can be used to
control the slew rate seen at the gate, thereby providing some
control of the di/dt and dv/dt of the voltage at the SA, SB, and SC
terminals. When GLx is set high, the upper half of the driver is
turned on and the drain sources current to the gate of the respec-
tive low-side MOSFET in the external power bridge, turning on
the MOSFET. When GLx is set low, the lower half of the driver is
turned on and the drain sinks current from the external MOSFET
gate circuit to the LSS terminal, turning off the MOSFET. LSS is
the low-side return path for discharge of the capacitance on the
MOSFET gates. It should be connected to the common sources of
the low-side external MOSFETs through a low-impedance circuit
board trace.
High-side gate drive
The high-side gate drive outputs GHA, GHB and GHC are ref-
erenced to the SA, SB, and SC pins respectively. These outputs
are designed to drive external N-channel power MOSFETs.
External resistors between each gate drive output and the gate
connection to the respective MOSFET (as close as possible to the
MOSFET) can be used to control the slew rate seen at the gate,
thereby controlling the di/dt and dv/dt of the voltage at the SA,
SB, and SC terminals. When GHx is set high, the upper half of
the driver is turned on and the drain sources current to the gate of
the respective high-side MOSFET in the external motor-driving
bridge, turning on the MOSFET. When GHx is set low, the lower
half of the driver is turned on and the drain sinks current from the
external MOSFET gate circuit to the respective Sx terminal, turn-
ing off the MOSFET.
The CA, CB, and CC pins are the positive supplies for the float-
ing high-side gate drives. The bootstrap capacitors are connected
between the Cx and Sx terminals of the same phase. The boot-
strap capacitors are charged to approximately V REG when the
associated output Sx terminal is low. When the Sx output swings
high, the charge on the bootstrap capacitor causes the voltage at
the corresponding Cx terminal to rise with the output to provide
the boosted gate voltage needed for the high-side MOSFETs.
The SA, SB, and SC terminals are connected directly to the motor
phase connections. These terminals sense the voltages switched
across the load. They are also connected to the negative side of
the bootstrap capacitors and are the negative supply connections
for the floating high-side drives. The discharge current from the
high-side MOSFET gate capacitance flows through these con-
nections which should have low impedance circuit board traces
to the MOSFET bridge. These terminals also provide the phase
voltage feedback to used to determine the rotor position.
Dead Time
To prevent cross conduction (shoot through) in any phase of the
power MOSFET bridge, it is necessary to have a dead-time delay
between a high- or low-side turn-off and the next complementary
turn-on event. The potential for cross conduction occurs when
any complementary high-side and low-side pair of MOSFETs
are switched at the same time, for example, at the PWM
switchpoints. In the A4960, the dead time for all three phases is
set by the contents of DT[5:0] (Config0 bits 5:0 ). These six bits
contain a positive integer that determines the dead time by divi-
sion from the system clock.
The dead time is defined as:
t DEAD = n × 50 ns (1)
where n is a positive integer defined by DT[5:0] and t DEAD has a
minimum programmable value of 100 ns.
For example, when DT[5:0] contains 011000 (24 in decimal),
then t DEAD = 1.2 μs (typical).
The accuracy of t DEAD is determined by the accuracy of the
system clock, as defined in the Electrical Characteristics table,
t OSC . A DT[5:0] value of 000000, 000001, or 000010 (0, 1, or 2
in decimal) sets the minimum programmable t DEAD of 100 ns.
Sleep Mode and RESETN
RESETN is an active-low input which allows the A4960 to enter
sleep mode, in which the current consumption from the VBB and
VDD supplies is reduced to its minimum level. When RESETN
is held low for longer than the reset pulse time, t RES , the inter-
nal pump regulator and all internal circuitry is disabled and the
A4960 enters sleep mode. In sleep mode the latched faults and
corresponding fault flags are cleared.
When coming out of sleep mode, the protection logic ensures
that the gate drive outputs are off until the charge pump reaches
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
17
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