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参数资料
| 型号： | A4960KJPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 22/35页 |
| 文件大小： | 0K |
| 描述： | IC BLDC CTLR BRUSHLESS 32LQFP |
| 标准包装： | 1 |
| 系列： | * |
| 应用： | * |
| 输出数： | * |
| 电流 - 输出： | * |
| 电压 - 负载： | * |
| 电源电压： | * |
| 工作温度： | * |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP 裸露焊盘 |
| 供应商设备封装： | 32-LQFP（7x7） |
| 包装： | 标准包装 |
| 其它名称： | 620-1452-6 |
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A4960
Automotive, Sensorless BLDC Controller
tion in some way, so as to prevent overtemperature damage to the
chip and unpredictable device operation. When the temperature
drops below T JF by more than the hysteresis value, T JFHys , the
general fault output flag (DIAG pin) goes high, but the overtem-
perature bit, TS, and FF remain set in the Diagnostic register until
cleared.
Chip Fault State : VREG Undervoltage
The internal charge-pump regulator supplies the low-side gate
driver and the bootstrap charge current. Before enabling any
of the outputs, it is critical to ensure that the regulated voltage,
V REG , at the VREG terminal is sufficiently high.
If V REG goes below the VREG Undervoltage Threshold,
V REGUVOFF , the general fault output flag (DIAG pin) goes low
and the VREG undervoltage bit, VR (Diagnostic bit 13) and the
common Fault flag bit, FF (bit 15), are set to 1. All gate drive
outputs go low, the motor drive is disabled, and the motor coasts.
When V REG rises above V REGUVON , the gate drive outputs are re-
enabled and the general fault output flag (DIAG pin) goes high.
The fault bit, VR, and FF remain set in the Diagnostic register
until cleared.
The VREG undervoltage monitor circuit is active during power-
up. The general fault output flag (DIAG pin) is low and all gate
drives will be low until V REG is greater than approximately 8 V.
Note that this is sufficient to turn on standard-threshold, external
power MOSFETs at a battery voltage as low as 5.5 V, but the
on-resistance of the MOSFET may be higher than its specified
maximum.
Chip Fault State: VDD Undervoltage
The logic supply voltage, V DD , at the VDD terminal is monitored
to ensure correct logical operation. If V DD drops below the VDD
Undervoltage Threshold, V DDUV , then the logical function of
the A4960 cannot be guaranteed and the outputs will be imme-
diately disabled. The A4960 will enter a power-down state and
all internal activity, other than the V DD voltage monitor, will be
suspended.
When V DD rises above the rising undervoltage threshold, V DDUV
+ V DDUVHys , the A4960 will perform a power-on reset. All serial
control registers will be reset to their power-on state, all fault
conditions and fault-specific bits in the Diagnostic register will be
reset, and the general fault output flag (DIAG pin) will go high.
The FF bit and the POR bit (Diagnostic bits 15 and 14) will be set
to 1 to indicate that a power-on reset has taken place.
The same power-on reset sequence occurs for initial power-on,
and also for a V DD “brown-out,” where V DD drops below V DDUV
only momentarily.
Bootstrap Undervoltage Fault State
In addition to a monitor on V REG , the A4960 also monitors the
individual bootstrap capacitor charge voltages to ensure sufficient
high-side drive. Before a high-side drive can be turned on, the
bootstrap capacitor voltage must be higher than the turn-on volt-
age limit, V BOOTUV + V BOOTUVHys . If this is not the case, then the
A4960 will attempt to charge the bootstrap capacitor by activat-
ing the complementary low-side drive. Under normal circum-
stances this will charge the capacitor above the turn-on voltage in
a few microseconds and the high-side drive will then be enabled.
The bootstrap voltage monitor remains active while the high-
side drive is active, and if the voltage drops below the turn-off
voltage, V BOOTUV , a charge cycle is also initiated. In either case,
if there is a fault that prevents the bootstrap capacitor charg-
ing, then the charge cycle will time out, the general fault output
flag (DIAG pin) will go low, and the outputs will be disabled.
The appropriate bit (VA, VB, or VC, according to the phase) in
the Diagnostic register will be set to allow the faulty bootstrap
capacitor to be determined by reading the serial data word from
the Diagnostic register.
The bootstrap undervoltage fault state will be latched until
RESETN is set low, a serial interface read is completed, or a
power-on reset occurs due to a V DD undervoltage on the logic
supply.
MOSFET fault detection
Faults on external MOSFETs are determined by measuring the
drain-source voltage of the MOSFET and comparing it to the
Drain-Source Threshold Voltage, V DSTH , defined by VT[5:0]
(Config1 bits 5:0). These bits provide the input to a 6-bit DAC
with a least significant bit value of typically 25 mV. The output of
the DAC produces V DSTH , defined as approximately:
V DSTH ?≈? n × 25 mV (6)
where n is a positive integer defined by VT[5:0].
For example, when VT[5:0] contains 101000 (40 in decimal),
then V DSTH = 1 V typically. The accuracy of V DSTH is defined in
the Electrical Characteristics table.
The low-side drain-source voltage for any MOSFET is mea-
sured between the LSS terminal and the appropriate Sx terminal.
Using the LSS terminal rather than the ground connection avoids
adding any low-side current sense voltage to the real low-side
drain-source voltage. The high-side drain-source voltage for
any MOSFET is measured between the VBRG terminal and the
appropriate Sx terminal. Using the VBRG terminal rather than the
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
21
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