参数资料
型号: A4960KJPTR-T
厂商: Allegro Microsystems Inc
文件页数: 20/35页
文件大小: 0K
描述: IC BLDC CTLR BRUSHLESS 32LQFP
标准包装: 1
系列: *
应用: *
输出数: *
电流 - 输出: *
电压 - 负载: *
电源电压: *
工作温度: *
安装类型: 表面贴装
封装/外壳: 32-LQFP 裸露焊盘
供应商设备封装: 32-LQFP(7x7)
包装: 标准包装
其它名称: 620-1452-6
A4960
Automotive, Sensorless BLDC Controller
The accuracy of t OFF is determined by the accuracy of the system
clock, t OSC , as defined in the Electrical Characteristics table. A
value of 00000 in PT[4:0] sets the minimum off-time of 10 μs.
Blank time
When the bridge is switched into the drive configuration, a
current spike occurs due to the reverse-recovery currents of
the clamp diodes and switching transients related to distributed
capacitance in the load. To prevent this current spike from being
detected as a current limit trip, the current-control compara-
tor output is blanked for a short period of time when the source
driver is turned on. The length of the blanking time is set by the
contents of BT[3:0] (Config0 bits 9:6). These four bits contain a
positive integer that determines the blank time derived by divi-
sion from the system clock.
The blank time is defined as:
t BL = n × 400 ns (5)
where n is a positive integer defined by BT[3:0].
For example, when BT[3:0] contains 1011 (11 in decimal), then
t BL = 4.4 μs typically.
The accuracy of t BL is determined by the accuracy of the system
clock, t OSC , as defined in the Electrical Characteristics table.
The blank time is also used with the MOSFET drain-source
monitors, which are used to determine MOSFET short faults.
The blank time is used in these circuits, as shown in figure 4, to
mask the effect of any voltage or current transients caused by any
PWM switching action.
The user must ensure that blank time is long enough to mask any
current transient seen by the internal sense amplifier and mask
any voltage transients seen by the drain-source monitors.
Diagnostics
Several diagnostic features are integrated into the A4960 to
provide indication of fault conditions. In addition to system-wide
faults such as undervoltage and overtemperature, the A4960
integrates individual drain-source monitors for each external
MOSFET, to provide short circuit detection.
The fault status is available from two sources, the DIAG output
terminal and the serial interface.
DIAG pin
The DIAG terminal is a diagnostic output that can be pro-
grammed through the serial interface DG[1:0](Run bits 5:4) to
provide any one of four alternative dedicated diagnostic signals:
? the general fault output flag
? the Sensorless Operation Indicator
? the programmed V DS threshold voltage
? a clock signal derived from the internal chip clock
After a power-on reset the DIAG output defaults to the fault out-
put flag. The general logic-level fault output flag outputs a low
on the DIAG pin to indicate a fault is present. This fault output
flag remains low while an unlatched fault is present or if one of
the latched faults has been detected and the outputs are disabled.
(Note there also is a common Fault flag, described in the Serial
fault output section.)
The Sensorless Operation Indicator is a logic level signal that is
set high when the A4960 has achieved sensorless commutation.
The Sensorless Operation Indicator is set low before sensorless
operation is achieved at start-up, or if sensorless operation is lost
while the motor should be operating. This indicator is held high
even when the motor is stopped, by setting RUN (Run bit 0) to 0
or BRK (Run bit 2) to 1.
The VDS threshold output provides access to the internal thresh-
old voltage to allow more precise calibration of the MOSFET
fault monitor threshold if required.
The clock output provides a logic-level square wave output to
allow more precise calibration of the timing settings if required.
Serial interface fault output
The serial interface allows detailed diagnostic information to be
read from the Diagnostic register at any time.
The first bit (bit 15) of the Diagnostic register contains the com-
mon Fault flag, FF, which is set high when any of the fault bits in
the Diagnostic register have been set. This allows fault conditions
to be detected using the serial interface by simply taking STRN
low. As soon as STRN goes low the fist bit in the Diagnostic
register can be read to determine if a fault has been detected at
any time since the last Diagnostic register reset. In all cases the
fault bits in the Diagnostic register are latched and only cleared
after a Diagnostic register reset (see Diagnostic Register section
on serial access).
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
19
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