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参数资料
| 型号： | A4960KJPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 26/35页 |
| 文件大小： | 0K |
| 描述： | IC BLDC CTLR BRUSHLESS 32LQFP |
| 标准包装： | 1 |
| 系列： | * |
| 应用： | * |
| 输出数： | * |
| 电流 - 输出： | * |
| 电压 - 负载： | * |
| 电源电压： | * |
| 工作温度： | * |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP 裸露焊盘 |
| 供应商设备封装： | 32-LQFP（7x7） |
| 包装： | 标准包装 |
| 其它名称： | 620-1452-6 |
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A4960
Automotive, Sensorless BLDC Controller
Mask This register contains a fault masking bit for each fault
bit in the Diagnostic register. If a bit is set to one in the Mask
register then the corresponding diagnostic will be completely
disabled. No fault states for the disabled diagnostic will be gener-
ated and no fault flags or diagnostic bits will be set.
Run This register contains various bits to set running conditions:
? BH[1:0], 2 bits to select the BEMF hysteresis.
? BW[2:0], 3 bits to select the BEMF window.
? ESF, the Enable Stop on Fault bit; defines the action taken
when a short is detected. See Diagnostics section for details of
fault actions.
? DG[1:0], 2 bits to select the output routed to the DIAG termi-
nal. The default output is the general fault output flag, which
is a low true (active low) signal that is active anytime a fault
is present or a fault state has been latched. The second option
sets the DIAG output high whenever the A4960 is running with
sensorless commutation. The other two outputs provide an ex-
ternal controller with the facility to read back the drain-source
threshold voltage, or to measure the system clock frequency for
calibration.
? RSC, the Restart control bit.
? When set to 1 allows restart after loss of BEMF synchroniza-
tion if RUN is 1 and BRK is 0.
? When set to 0 the motor will coast to a stop when bemf syn-
chronization is lost.
? BRK, brake control.
? DIR, direction control.
? RUN, enables the A4960 to start and run the motor.
Diagnostic register
There is one diagnostic register in addition to the eight writable
registers. Each time a register is written, the Diagnostic register
can be read, MSB first, on the serial output terminal, SDO (see
serial timing diagram, figure 1). The Diagnostic register contains
fault flags for each fault condition and a general fault flag. When-
ever a fault occurs, the corresponding flag bit in the Diagnostic
register will be set and latched.
The fault flags in the Diagnostic register are reset only on the
completion of a serial interface access, or when the RESETN
input is low for the Reset Pulse Width, t RES . Resetting the
Diagnostic register only affects latched faults that are no longer
present. For any static faults that are still present, for example
overtemperature, the fault flag will remain set after the register
reset.
At power-up or after a power-on reset, the FF bit and the POR bit
are set and all other bits are reset. This indicates to the external
controller that a power-on reset has taken place and all registers
have been reset. Note that a power-on reset only occurs when the
VDD supply rises above its undervoltage threshold. Power-on
reset is not affected by the state of the VBB supply or VREG.
The first bit in the register is the diagnostic register flag, FF. This
is high if any bits in the diagnostic register are set or if a serial
write error has occurred. When STRN goes low to start a serial
write SDO comes out of its high impedance state and outputs
the serial register fault flag. This allows the main controller to
poll the A4960 through the serial interface to determine if a fault
has been detected. If no faults have been detected then the serial
transfer may be terminated without generating a serial read fault
by ensuring that SCK remains high while STRN is low. When
STRN goes high the transfer will be terminated and SDO will go
into its high impedance state.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
25
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