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参数资料
| 型号： | A4960KJPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 24/35页 |
| 文件大小： | 0K |
| 描述： | IC BLDC CTLR BRUSHLESS 32LQFP |
| 标准包装： | 1 |
| 系列： | * |
| 应用： | * |
| 输出数： | * |
| 电流 - 输出： | * |
| 电压 - 负载： | * |
| 电源电压： | * |
| 工作温度： | * |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP 裸露焊盘 |
| 供应商设备封装： | 32-LQFP（7x7） |
| 包装： | 标准包装 |
| 其它名称： | 620-1452-6 |
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A4960
Automotive, Sensorless BLDC Controller
Serial Interface Description
A three wire synchronous serial interface, compatible with SPI,
is used to control the features of the A4960. A fourth wire can
be used to provide diagnostic feedback and read back of register
contents.
The A4960 can be started only by using the serial interface to set
the RUN bit (Run bit 0) to 1. Application specific settings are
configured by setting the appropriate register bits through the
serial interface.
The serial interface timing requirements are specified in the
Electrical Characteristics table, and illustrated in figure 1. Data is
received on the SDI terminal and clocked through a shift register
on the rising edge of the clock signal input on the SCK terminal.
STRN is normally held high, and is brought low only to initiate a
serial transfer. No data is clocked through the shift register when
STRN is high, allowing multiple slave units to use common SDI,
Table 3. Serial Registers Definition
SCK, and SDO connections. Each slave then requires an indepen-
dent STRN connection.
When 16 data bits have been clocked into the shift register,
STRN must be taken high to latch the data into the selected regis-
ter. When this occurs, the internal control circuits act on the new
data and the Diagnostic register is reset.
If there are more than 16 rising edges on SCK, or if STRN goes
high and there are fewer than 16 rising edges on SCK, the write
will be cancelled without writing data to the registers. In addition
the Diagnostic register will not be reset and the FF bit (Diagnotic
bit 15) will be set to 1 to indicate a data transfer error.
Diagnostic information or the contents of the configuration and
control registers is output on the SDO terminal, MSB first, while
STRN is low. The output stream changes to the next bit on each
falling edge of SCK. The first bit, which is always the FF bit, is
output as soon as STRN goes low.
1 5
1 4
1 3
1 2
1 1
1 0
9
8
7
6
5
4
3
2
1
0
Config 0 (Blank,Dead)
0
0
0
WR
CB1
CB0
BT3
BT2
BT1
BT0
DT5
DT4
DT3
DT2
DT1
DT0
0
0
1
0
0
0
0
1
0
1
0
0
Config 1 (V REF ,V DSTH )
0
0
1
WR
VR3
VR2
VR1
VR0
VT5
VT4
VT3
VT2
VT1
VT0
Config 2 (PWM)
0
1
0
WR
0
0
0
0
1
0
1
0
1
0
1
0
1
0
0
PT4
1
0
PT3
0
0
PT2
0
0
PT1
0
0
PT0
0
Config 3 (Hold)
Config 4 (Start Com)
0
1
1
0
1
0
WR
WR
0
0
0
0
0
0
IDS
0
0
HQ3
0
EC3
1
HQ2
1
EC2
1
HQ1
0
EC1
1
HQ0
1
EC0
1
HT3
0
SC3
0
HT3
1
SC2
1
HT1
0
SC1
0
HT0
0
SC0
0
Config 5 (Ramp)
1
0
1
WR
PA3
PA2
PA1
PA0
RQ3
RQ2
RQ1
RQ0
RR3
RR2
RR1
RR0
0
0
0
0
1
0
0
0
0
0
0
0
Mask
1
1
0
WR
TW
TS
LOS
VA
VB
VC
AH
AL
BH
BL
CH
CL
0
0
0
0
0
0
0
0
0
0
0
0
Run
1
1
1
WR
BH1
BH0
BW2
BW1
BW0
ESF
DG1
DG0
RSC
BRK
DIR
RUN
0
0
1
0
0
0
0
0
0
0
0
0
Diagnostic
FF
POR
VR
TW
TS
LOS
VA
VB
VC
AH
AL
BH
BL
CH
CL
1 1 0 0 0 0
*Power-on reset value shown below each input register bit.
0
0
0
0
0
0
0
0
0
0
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
23
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