参数资料
| 型号： | AD14060LBF-4 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 25/48页 |
| 文件大小： | 0K |
| 描述： | IC DSP CMOS 32BIT 308CQFP |
| 产品培训模块： | SHARC Processor Overview |
| 标准包装： | 1 |
| 系列： | SHARC® |
| 类型： | 浮点 |
| 接口： | 主机接口，连接端口，串行端口 |
| 时钟速率： | 40MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 2MB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 3.30V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 308-CBQFP |
| 供应商设备封装： | 308-CQFP（52x52） |
| 包装： | 托盘 |
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AD14060/AD14060L
Rev. B | Page 31 of 48
Pin
Type1
Function
SBTS
I/S
Suspend Bus Three-State (common to all SHARCs). External devices can assert SBTS (low) to place the external bus
address, data, selects, and strobes in a high impedance state for the following cycle. If the AD14060/AD14060L
attempts to access external memory while SBTS is asserted, the processor halts and the memory access does not
complete until SBTS is de-asserted. SBTS should be used only to recover from host processor/AD14060/AD14060L
deadlock, or used with a DRAM controller.
HBR
I/A
Host Bus Request (common to all SHARCs). Must be asserted by a host processor to request control of the
AD14060/AD14060L’s external bus. When HBR is asserted in a multiprocessing system, the ADSP-2106x that is bus
master relinquishes the bus and asserts HBG. To relinquish the bus, the ADSP-2106x places the address, data, select,
and strobe lines in a high impedance state. HBR has priority over all ADSP-2106x bus requests (BR6-1) in a
multiprocessing system.
HBG
I/O
Host Bus Grant (common to all SHARCs). Acknowledges an HBR bus request, indicating that the host processor can
take control of the external bus. HBG is asserted (held low) by the AD14060/AD14060L until HBR is released. In a
multiprocessing system, HBG is output by the ADSP-2106x bus master and is monitored by all others.
CSA
I/A
Chip Select. Asserted by host processor to select SHARC_A.
CSB
I/A
Chip Select. Asserted by host processor to select SHARC_B.
CSC
I/A
Chip Select. Asserted by host processor to select SHARC_C.
CSD
I/A
Chip Select. Asserted by host processor to select SHARC_D.
REDY
(O/D)
O
Host Bus Acknowledge (common to all SHARCs). The AD14060/AD14060L de-asserts REDY (low) to add wait states
to an asynchronous access of its internal memory or IOP registers by a host. Open-drain output (O/D) by default;
can be programmed in ADREDY bit of SYSCON register of individual ADSP-21060s to be active drive (A/D). REDY is
output only if the CS and HBR inputs are asserted.
BR6-1
I/O/S
Multiprocessing Bus Requests (common to all SHARCs). Used by multiprocessing ADSP-2106xs to arbitrate for bus
mastership. An ADSP-2106x drives only its own BRx line (corresponding to the value of its ID2-0 inputs) and
monitors all others. In a multiprocessor system with less than six ADSP-2106xs, the unused BRx pins should be
pulled high; BR4-1 must not be pulled high or low, because they are outputs.
RPBA
I/S
Rotating Priority Bus Arbitration Select (common to all SHARCs). When RPBA is high, rotating priority for multi-
processor bus arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system
configuration selection that must be set to the same value on every ADSP-2106x. If the value of RPBA is changed
during system operation, it must be changed in the same CLKIN cycle on every ADSP-2106x.
CPAy (O/D)
I/O
Core Priority Access (y = SHARC_A, B, C, D). Asserting its CPA pin allows the core processor of an ADSP-2106x bus
slave to interrupt background DMA transfers and gain access to the external bus. CPA is an open-drain output that
is connected to all ADSP-2106xs in the system, if this function is required. The CPA pin of each internal ADSP-21060
is brought out individually. The CPA pin has an internal 5 k pull-up resistor. If core access priority is not required in
a system, the CPA pin should be left unconnected.
DT0
O/T
Data Transmit (common Serial Ports 0 to all SHARCs, TDM). The DT pin has a 50 k internal pull-up resistor.
DR0
I
Data Receive (common Serial Ports 0 to all SHARCs, TDM). The DR pin has a 50 k internal pull-up resistor.
TCLK0
I/O
Transmit Clock (common Serial Ports 0 to all SHARCs, TDM). The TCLK pin has a 50 k internal pull-up resistor.
RCLK0
I/O
Receive Clock (common Serial Ports 0 to all SHARCs, TDM). The RCLK pin has a 50 k internal pull-up resistor.
TFS0
I/O
Transmit Frame Sync (common Serial Ports 0 to all SHARCs, TDM).
RFS0
I/O
Receive Frame Sync (common Serial Ports 0 to all SHARCs, TDM).
DTy1
O/T
Data Transmit (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D). The DT pin has a 50 k
internal pull-up resistor.
DRy1
I
Data Receive (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D). The DR pin has a 50 k
internal pull-up resistor.
TCLKy1
I/O
Transmit Clock (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D). The TCLK pin has a 50 k
internal pull-up resistor.
RCLKy1
I/O
Receive Clock (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D). The RCLK pin has a 50 k
internal pull-up resistor.
TFSy1
I/O
Transmit Frame Sync (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D).
RFSy1
I/O
Receive Frame Sync (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D).
FLAGy0
I/O/A
Flag Pins (FLAG0 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D). Each pin is configured via control bits
as either an input or an output. As an input, it can be tested as a condition. As an output, it can be used to signal
external peripherals.
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