参数资料
| 型号： | AD14060LBF-4 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 44/48页 |
| 文件大小： | 0K |
| 描述： | IC DSP CMOS 32BIT 308CQFP |
| 产品培训模块： | SHARC Processor Overview |
| 标准包装： | 1 |
| 系列： | SHARC® |
| 类型： | 浮点 |
| 接口： | 主机接口，连接端口，串行端口 |
| 时钟速率： | 40MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 2MB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 3.30V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 308-CBQFP |
| 供应商设备封装： | 308-CQFP（52x52） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页当前第44页第45页第46页第47页第48页
AD14060/AD14060L
Rev. B | Page 5 of 48
TIMING SPECIFICATIONS
This data sheet represents production-released specifications
for the AD14060 (5 V), and for the AD14060L (3.3 V). The
ADSP-21060 die components are 100% tested, and the
assembled AD14060/AD14060L units are again extensively
tested at speed and across temperature. Parametric limits were
established from the ADSP-21060 characterization followed by
further design and analysis of the AD14060/AD14060L package
characteristics.
The specifications are based on a CLKIN frequency of 40 MHz
(tCK = 25 ns). The DT derating allows specifications at other
CLKIN frequencies (within the minimum to maximum range
between the actual CLKIN period and a CLKIN period of 25 ns:
DT = tCK 25 ns
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, one
cannot meaningfully add parameters to derive longer times.
Switching Characteristics specify how the processor changes its
signals. The user has no control over this timing—circuitry
external to the processor must be designed for compatibility
with these signal characteristics. Switching characteristics
specify what the processor does in a given circumstance. The
user can also use switching characteristics to ensure that any
timing requirement of a device connected to the processor
(such as memory) is satisfied.
Timing Requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. Timing requirements guarantee that the
processor operates correctly with other devices.
(O/D) = Open Drain
(A/D) = Active Drive
Table 3. Clock Input
40 MHz (5 V)
40 MHz (3.3 V)
Parameter
Min
Max
Min
Max
Unit
Clock Input
Timing Requirements:
tCK
CLKIN Period
25
100
25
100
ns
tCKL
CLKIN Width Low
7
9.5
ns
tCKH
CLKIN Width High
5
ns
tCKRF
CLKIN Rise/Fall (0.4 V to 2.0 V)
3
ns
CLKIN
tCKH
tCKL
tCK
00667-011
Figure 2. Clock Input
相关PDF资料 |
PDF描述 |
|---|---|
| AD1833AASTZ-REEL | IC DAC AUDIO 24BIT 6CH 48LQFP |
| AD1835AASZ | IC CODEC 2ADC/8DAC 24BIT 52-MQFP |
| AD1836ACSZ | IC CODEC 4ADC/6DAC 24 BIT 52MQFP |
| AD1838AASZ | IC CODEC 2ADC/6DAC 24 BIT 52MQFP |
| AD1851RZ-J | IC DAC AUDIO FASTSET 16B 16SOIC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD14160 | 制造商:AD 制造商全称:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family |
| AD14160BB-4 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD14160KB-4 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD14160L | 制造商:AD 制造商全称:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family |
| AD14160LBB-4 | 制造商:AD 制造商全称:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family |
发布紧急采购，3分钟左右您将得到回复。