参数资料
| 型号： | AD14060LBF-4 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 26/48页 |
| 文件大小： | 0K |
| 描述： | IC DSP CMOS 32BIT 308CQFP |
| 产品培训模块： | SHARC Processor Overview |
| 标准包装： | 1 |
| 系列： | SHARC® |
| 类型： | 浮点 |
| 接口： | 主机接口，连接端口，串行端口 |
| 时钟速率： | 40MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 2MB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 3.30V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 308-CBQFP |
| 供应商设备封装： | 308-CQFP（52x52） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页当前第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页
AD14060/AD14060L
Rev. B | Page 32 of 48
Pin
Type1
Function
FLAG1
I/O/A
Flag Pins (FLAG1 common to all SHARCs). This pin is configured via control bits internal to individual ADSP-21060s
as either an input or an output. As an input, it can be tested as a condition. As an output, it can be used to signal
external peripherals.
FLAGy2
I/O/A
Flag Pins (FLAG2 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D). Each pin is configured via control bits
as either an input or an output. As an input, it can be tested as a condition. As an output, it can be used to signal
external peripherals.
IRQy2-0
I/A
Interrupt Request Lines (individual IRQ2-0 from y = SHARC_A, SHARC_B, SHARC_C, SHARC_D). Can be either edge-
triggered or level-sensitive.
DMAR1
I/A
DMA Request 1 (DMA Channel 7). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
DMAR2
I/A
DMA Request 2 (DMA Channel 8). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
DMAG1
O/T
DMA Grant 1 (DMA Channel 7). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
DMAG2
O/T
DMA Grant 2 (DMA Channel 8). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
LyxCLK
I/O
Link Port Clock (y = SHARC_A, B, C, D; x = Link Ports 1, 3, 4)2. Each LyxCLK pin has a 50 k internal pull-down resistor
that is enabled or disabled by the LPDRD bit of the LCOM register of the ADSP-20160.
LyxDAT3-0
I/O
Link Port Data (y = SHARC_A, B, C, D; x = Link Ports 1, 3, 4)2. Each LyxDAT pin has a 50 k internal pull-down resistor
that is enabled or disabled by the LPDRD bit of the LCOM register of the ADSP-21060.
LyxACK
I/O
Link Port Acknowledge (y = SHARC_A, B, C, D; x = Link Ports 1, 3, 4)2. Each LyxACK pin has a 50 k internal pull-
down resistor that is enabled or disabled by the LPDRD bit of the LCOM register of the ADSP-21060.
EBOOTA
I
EPROM Boot Select (SHARC_A). When EBOOTA is high, SHARC_A is configured for booting from an 8-bit EPROM.
When EBOOTA is low, the LBOOTA and BMSA inputs determine booting mode for SHARC_A. See the following
table. This signal is a system configuration selection that should be hardwired.
LBOOTA
I
Link Boot. When LBOOTA is high, SHARC_A is configured for link port booting. When LBOOTA is low, SHARC_A is
configured for host processor booting or no booting. See the following table. This signal is a system configuration
selection that should be hardwired.
BMSA
Boot Memory Select. When this pin is an output, it is used as chip select for boot EPROM devices (when EBOOTA =
1, LBOOTA = 0). In a multiprocessor system, BMS is output by the bus master. As an input, when low, this pin
indicates that no booting is to occur and that SHARC_A is to begin executing instructions from external memory.
See the following table. This input is a system configuration selection that should be hardwired.
EBOOTBCD
I
EPROM Boot Select (common to SHARC_B, SHARC_C, SHARC_D). When EBOOTBCD is high, SHARC_B, C, and D are
configured for booting from an 8-bit EPROM. When EBOOTBCD is low, the LBOOTBCD and BMSBCD inputs
determine booting mode for SHARC_B, C, and D. See the following table. This signal is a system configuration
selection that should be hardwired.
LBOOTBCD
I
LINK Boot (common to SHARC_B, SHARC_C, SHARC_D). When LBOOTBCD is high, SHARC_B, C, and D are configured
for link port booting. When LBOOTBCD is low, SHARC_B, C, and D are configured for host processor booting or no
booting. See the following table. This signal is a system configuration selection that should be hardwired.
BMSBCD
I/O/T3
Boot Memory Select. When this pin is an output, it is used as chip select for boot EPROM devices (when EBOOTBCD
= 1, LBOOTBCD = 0). In a multiprocessor system, BMS is output by the bus master. As an input, when low, this pin
indicates that no booting is to occur and that SHARC_B, C, and D are to begin executing instructions from external
memory. See table below. This input is a system configuration selection that should be hardwired.
EBOOT
LBOOT
BMS
Booting Mode
1
0
Output
EPROM (connect BMS to EPROM chip select).
0
1 (Input)
Host processor.
0
1
1 (Input)
Link port.
0
0 (Input)
No booting. Processor executes from external memory.
0
1
0 (Input)
Reserved.
1
x (Input)
Reserved.
TIMEXPy
O
Timer Expired (individual TIMEXP from y = SHARC_A, SHARC_B, SHARC_C, SHARC_D). Asserted for four cycles when
the timer is enabled and TCOUNT decrements to 0.
CLKIN
I
Clock In (common to all SHARCs). External clock input to the AD14060/AD14060L. The instruction cycle rate is equal
to CLKIN. CLKIN cannot be halted, changed, or operated below the minimum specified frequency.
RESET
I/A
Module Reset (common to all SHARCs). Resets the AD14060/AD14060L to a known state. This input must be
asserted (low) at power-up.
TCK
I
Test Clock (JTAG) (common to all SHARCs). Provides an asynchronous clock for JTAG boundary scan.
TMS
I/S
Test Mode Select (JTAG) (common to all SHARCs). Used to control the test state machine. TMS has a 20 k internal
pull-up resistor.
相关PDF资料 |
PDF描述 |
|---|---|
| AD1833AASTZ-REEL | IC DAC AUDIO 24BIT 6CH 48LQFP |
| AD1835AASZ | IC CODEC 2ADC/8DAC 24BIT 52-MQFP |
| AD1836ACSZ | IC CODEC 4ADC/6DAC 24 BIT 52MQFP |
| AD1838AASZ | IC CODEC 2ADC/6DAC 24 BIT 52MQFP |
| AD1851RZ-J | IC DAC AUDIO FASTSET 16B 16SOIC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD14160 | 制造商:AD 制造商全称:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family |
| AD14160BB-4 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD14160KB-4 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD14160L | 制造商:AD 制造商全称:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family |
| AD14160LBB-4 | 制造商:AD 制造商全称:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family |
发布紧急采购，3分钟左右您将得到回复。