参数资料
| 型号： | AD14060LBF-4 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 32/48页 |
| 文件大小： | 0K |
| 描述： | IC DSP CMOS 32BIT 308CQFP |
| 产品培训模块： | SHARC Processor Overview |
| 标准包装： | 1 |
| 系列： | SHARC® |
| 类型： | 浮点 |
| 接口： | 主机接口，连接端口，串行端口 |
| 时钟速率： | 40MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 2MB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 3.30V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 308-CBQFP |
| 供应商设备封装： | 308-CQFP（52x52） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页当前第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页
AD14060/AD14060L
Rev. B | Page 38 of 48
LINK PORT I/O
Each individual SHARC features six 4-bit link ports that
facilitate SHARC-to-SHARC communication and external I/O
interfacing. Each link port can be configured for either 1× or 2×
operation, allowing each to transfer either four or eight bits
per cycle.
The link ports can operate independently and simultaneously,
with a maximum bandwidth of 40 MBytes/s each, or a total of
240 MBytes/s per SHARC.
The AD14060/AD14060L optimizes the link port connections
internally, and brings a total of 12 of the link ports off-module
for user-defined system connections. Internally, each SHARC
has a connection to the other three SHARCs with a dedicated
link port interface. Thus, each SHARC can directly interface
with its nearest and next-nearest neighbor. The remaining three
link ports from each SHARC are brought out independently
from each SHARC. A maximum of 480 MBytes/s link port
bandwidth is then available off of the AD14060/AD14060L.
The link port connections are shown in Figure 25.
SHARC_A
SHARC_B
SHARC_D
SHARC_C
1
3
4
1
3
4
55
2
0
55
2
1
3
4
1
3
4
0
00667-006
Figure 25. Link Port Connections
Link Port 4, the boot-link port, is brought off independently
from each SHARC. Individual booting is then allowed, or
chained link-port booting is possible, as described in the
Multiprocessor Link-Port Booting section.
Link port data is packed into 32-bit or 48-bit words, and can be
directly read by the SHARC core processor or DMA transferred
to on-SHARC memory.
Each link port has its own double-buffered input and output
registers. Clock/acknowledge handshaking controls link port
transfers. Transfers are programmable as either transmit or
receive.
SERIAL PORTS
The SHARC serial ports provide an inexpensive interface to a
wide variety of digital and mixed-signal peripheral devices.
Each SHARC has two serial ports. The AD14060/AD14060L
provides direct access to Serial Port 1 of each SHARC. Serial
Port 0 is bused in common to each SHARC, and brought off-
module.
The serial ports can operate at the full clock rate of the module,
providing each with a maximum data rate of 40 Mbit/s.
Independent transmit and receive functions provide more
flexible communications. Serial port data can be automatically
transferred to and from on-SHARC memory via DMA, and
each of the serial ports offers time-division-multiplexed (TDM)
multichannel mode.
The serial ports can operate with little-endian or big-endian
transmission formats, with word lengths selectable from 3 bits
to 32 bits. They offer selectable synchronization and transmit
modes as well as optional -law or A-law companding. Serial
port clocks and frame syncs can be internally or externally
generated.
PROGRAM BOOTING
The AD14060/AD14060L supports automatic downloading of
programs following power-up or a software reset. The SHARC
offers the following options for program booting:
From an 8-bit EPROM
From a host processor
Through the link ports
No boot
In no-boot mode, the SHARC starts executing instructions
from Address 0x0040 0004 in external memory. The boot mode
is selected by the state of the following signals: BMS, EBOOT,
and LBOOT.
On the AD14060/AD14060L, SHARC_A’s boot mode is sepa-
rately controlled, while SHARC_B, C, and D are controlled as a
group. With this flexibility, the AD14060/AD14060L can be
configured to boot using any of the following methods.
Multiprocessor Host Booting
To boot multiple ADSP-21060 processors from a host, each
ADSP-21060 must have its EBOOT, LBOOT, and BMS pins
configured for host booting: EBOOT = 0, LBOOT = 0, and
BMS = 1. After system power-up, each ADSP-21060 is in the
idle state and the BRx bus request lines are de-asserted. The
host must assert the HBR input and boot each ADSP-21060 by
asserting its CS pin and downloading instructions.
相关PDF资料 |
PDF描述 |
|---|---|
| AD1833AASTZ-REEL | IC DAC AUDIO 24BIT 6CH 48LQFP |
| AD1835AASZ | IC CODEC 2ADC/8DAC 24BIT 52-MQFP |
| AD1836ACSZ | IC CODEC 4ADC/6DAC 24 BIT 52MQFP |
| AD1838AASZ | IC CODEC 2ADC/6DAC 24 BIT 52MQFP |
| AD1851RZ-J | IC DAC AUDIO FASTSET 16B 16SOIC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD14160 | 制造商:AD 制造商全称:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family |
| AD14160BB-4 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD14160KB-4 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD14160L | 制造商:AD 制造商全称:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family |
| AD14160LBB-4 | 制造商:AD 制造商全称:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family |
发布紧急采购，3分钟左右您将得到回复。