参数资料
| 型号： | AD14060LBF-4 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 7/48页 |
| 文件大小： | 0K |
| 描述： | IC DSP CMOS 32BIT 308CQFP |
| 产品培训模块： | SHARC Processor Overview |
| 标准包装： | 1 |
| 系列： | SHARC® |
| 类型： | 浮点 |
| 接口： | 主机接口，连接端口，串行端口 |
| 时钟速率： | 40MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 2MB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 3.30V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 308-CBQFP |
| 供应商设备封装： | 308-CQFP（52x52） |
| 包装： | 托盘 |
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AD14060/AD14060L
Rev. B | Page 15 of 48
ASYNCHRONOUS READ/WRITE—HOST TO AD14060/AD14060L
Use these specifications for asynchronous host processor access to an AD14060/AD14060L, after the host has asserted CS and HBR (low).
After HBG is returned by the AD14060/AD14060L, the host can drive the RD and WR pins to access the AD14060/AD14060L’s internal
memory or IOP registers. HBR and HBG are assumed low for this timing.
Table 13. Specifications
5 V
3.3 V
Parameter
Min
Max
Min
Max
Unit
Read Cycle
Timing Requirements:
tSADRDL
Address Setup/CS Low before RD Low1
0.5
ns
tHADRDH
Address Hold/CS Hold Low after RD
0.5
ns
tWRWH
RD/WR High Width
6
ns
tDRDHRDY
RD High Delay after REDY (O/D) Disable
0
ns
tDRDHRDY
RD High Delay after REDY (A/D) Disable
0
ns
Switching Characteristics:
tSDATRDY
Data Valid before REDY Disable from Low
1.5
ns
tDRDYRDL
REDY (O/D) or (A/D) Low Delay after RD Low
11
13.5
ns
tRDYPRD
REDY (O/D) or (A/D) Low Pulse Width for Read
45 + DT
ns
tHDARWH
Data Disable after RD High
1.5
9
1.5
9.5
ns
Write Cycle
Timing Requirements:
tSCSWRL
CS Low Setup before WR Low
0.5
ns
tHCSWRH
CS Low Hold after WR High
0.5
ns
tSADWRH
Address Setup before WR High
5.5
ns
tHADWRH
Address Hold after WR High
2.5
ns
tWWRL
WR Low Width
7
ns
tWRWH
RD/WR High Width
6
ns
tDWRHRDY
WR High Delay after REDY (O/D) or (A/D) Disable
0.5
ns
tSDATWH
Data Setup before WR High
5.5
ns
tHDATWH
Data Hold After WR High
1.5
ns
Switching Characteristics:
tDRDYWRL
REDY (O/D) or (A/D) Low Delay after WR/CS Low
11
13.5
ns
tRDYPWR
REDY (O/D) or (A/D) Low Pulse Width for Write
15
ns
tSRDYCK
REDY (O/D) or (A/D) Disable to CLKIN
0 + 7 DT/16
8 + 7 DT/16
0 + 7 DT/16
8 + 7 DT/16
ns
1 Not required, if RD and address are valid tHBGRCSV after HBG goes low. For first access after HBR is asserted, ADDR31–0 must be a non-MMS value 1/2 tCLK before RD or WR
goes low or by tHBGRCSV after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. For address bits to be driven
during asynchronous host accesses, see the ADSP-2106x SHARC User’s Manual.
CLKIN
REDY (O/D)
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
REDY (A/D)
tSRDYCK
00667-021
Figure 12. Synchronous REDY Timing
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