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参数资料
| 型号： | AD6634BBC |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 无绳电话/电话 |
| 英文描述： | 80 MSPS, Dual-Channel WCDMA Receive Signal Processor (RSP) |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA196 |
| 封装： | 15 MM X 15 MM, BGA-196 |
| 文件页数： | 31/52页 |
| 文件大小： | 925K |
| 代理商： | AD6634BBC |
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REV. 0
AD6634
–31–
spike in the signal level. If averaging of four samples is used, the
AGC will attack a sudden increase in signal level more slowly
compared to no averaging. The same would apply to the manner in
which the AGC would attack a sudden decrease in the signal level.
Desired Clipping Level Mode
As noted previously, each AGC can be configured so that the
loop locks on to a desired clipping level or a desired signal level.
The Desired Clipping Level mode can be selected by setting
Bit 4 of individual AGC control words (0x0A, 0x12). For sig-
nals that tend to exceed the bounds of the peak-to-average ratio,
the desired clipping level option allows a way to keep from truncat-
ing those signals and still provide an AGC that attacks quickly
and settles to the desired output level. The signal path for this
mode of operation is shown with broken arrows in the Func-
tional Block Diagram and the operation is similar to the desired
signal level mode.
First, the data from the gain multiplier is truncated to a lower
resolution (4, 5, 6, 7, 8, 10, 12, or 16 bits) as set by the AGC
control word. An error term (both I and Q) is generated that is
the difference between the signals before and after truncation.
This term is passed to the complex squared magnitude block,
for averaging and decimating the update samples and taking
their square root to find rms samples as in desired signal level
mode. In place of the request desired signal level, a desired
clipping level is subtracted, leaving an error term to be
processed by the second order loop filter. The rest of the loop
operates the same way as the desired signal level mode. This way
the truncation error is calculated and the AGC loop operates to
maintain a constant truncation error level.
Apart from Bit 4 of the AGC control words, the only register
setting changes compared to the Desired Signal level mode is
that the Desired Clipping level is stored in the AGC Desired
Level registers (0x0C, 0x15) instead of the Request Signal level
(as in Desired Signal Level mode).
Synchronization
In scenarios where AGC output is connected to a RAKE receiver,
the RAKE receiver can synchronize the average and update
section to update the average power for AGC error calculation
and loop filtering. This external sync signal synchronizes the
AGC changes to RAKE receiver and makes sure that the AGC
gain word does not change over a symbol period and thus more
accurate estimation. Such synchronization can be accomplished
by setting the appropriate bits of the AGC control register.
When the channel comes out of sleep, it loads the AGC hold-off
counter value and starts counting down, clocked by the Master
clock. When this counter reaches zero, the CIC filter of the
AGC starts decimation and updates the AGC loop filter based
on the CIC decimation value set.
Further, whenever the user wants to synchronize the start of
decimation for a new update sample, an appropriate hold-off
value can be set in AGC hold-off counter (0x0B, 0x13) and the
Sync now bit (Bit 3) in the AGC control word is set. Upon
setting this bit, the hold-off counter value is counted down and
a CIC decimated value is updated on the count of zero.
Along with updating a new value, the CIC filter accumulator
can be reset if Init on Sync bit (Bit 2) of the AGC control word
is set. Each sync will initiate a new sync signal unless first sync
only bit (Bit 1) of the AGC control word is set. If this bit is not
set, again the hold-off counter is loaded with the value in the
hold-off register to count down and repeat the same process.
These additional features make the AGC synchronization more
flexible and applicable to varied circumstances.
Addresses 0x0A–0x11 have been reserved for configuring AGC
A and addresses 0x12–0x19 have been reserved for configuring
AGC B. The register specifications are detailed in the Memory
Map for Output Port Control Registers section.
USER CONFIGURABLE BUILT-IN SELF-TEST (BIST)
The AD6634 includes two built-in test features to test the integrity
of each channel. The first is a RAM BIST (Built-In Self-Test)
and is intended to test the integrity of the high speed random
access memory within the AD6634. The second is Channel BIST,
which is designed to test the integrity of the main signal paths of
the AD6634. Each BIST function is independent of the other,
meaning that each channel can be tested independently at the
same time.
RAM BIST
The RAM BIST can be used to validate functionality of the
on-chip RAM. This feature provides a simple pass/fail test,
which will give confidence that the channel RAM is operational.
The following steps should be followed to perform this test.
1. The channels to be tested should be put into Sleep mode via
the external address register 0x011.
2. The RAM BIST Enable bit in the RCF register 0xA8 should
be set high.
3. Wait 1600 clock cycles.
4. Register 0xA8 should be read back. If Bit 0 is high, the test is
not yet complete. If Bit 0 is low, the test is complete and
Bits 1 and 2 indicate the condition of the internal RAM. If
Bit 1 is high, CMEM is bad. If Bit 2 is high, DMEM is bad.
Table VIII. BIST Register 0xA8
XA8
XX1
000
010
100
110
Coefficient MEM
Test Incomplete
Pass
Fail
Pass
Fail
Data MEM
Test Incomplete
Pass
Pass
Fail
Fail
Channel BIST
The Channel BIST is a thorough test of the selected AD6634
signal path. With this test mode, it is possible to use externally
supplied vectors or an internal pseudo-random generator. An
error signature register in the RCF monitors the output data of
the channel and is used to determine if the proper data exits the
RCF. If errors are detected, each internal block may be bypassed
and another test can be run to debug the fault. The I and Q paths
are tested independently. The following steps should be taken
to perform this test.
1. The channels to be tested should be configured as required
for the application setting the decimation rates, scalars, and
RCF coefficients.
2. The channels should remain in the Sleep mode.
3. The Start Hold-Off counter of the channels to be tested
should be set to 1.
4. Memory location 0xA5 and 0xA6 should be set to 0.
相关PDF资料 |
PDF描述 |
|---|---|
| AD6634PCB | 80 MSPS, Dual-Channel WCDMA Receive Signal Processor (RSP) |
| AD6635 | 4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP) |
| AD6635BB | 4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP) |
| AD6636 | 150 MSPS Wideband Digital Down-Converter (DDC) |
| AD6636BBCZ1 | 150 MSPS Wideband Digital Down-Converter (DDC) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD6634BBCZ | 功能描述:IC RSP 80MSPS DUAL 196CSPBGA RoHS:是 类别:RF/IF 和 RFID >> RF 混频器 系列:AD6634 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:100 系列:- RF 型:W-CDMA 频率:2.11GHz ~ 2.17GHz 混频器数目:1 增益:17dB 噪音数据:2.2dB 次要属性:- 电流 - 电源:11.7mA 电源电压:2.7 V ~ 3.3 V 包装:托盘 封装/外壳:12-VFQFN 裸露焊盘 供应商设备封装:12-QFN-EP（3x3） |
| AD6634BC/PCB | 制造商:Analog Devices 功能描述:WCDMA RECEIVE SGNL PROCESSOR - Bulk |
| AD6634PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:80 MSPS, Dual-Channel WCDMA Receive Signal Processor (RSP) |
| AD6635 | 制造商:AD 制造商全称:Analog Devices 功能描述:4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP) |
| AD6635BB | 功能描述:IC RSP 80MSPS QUAD 324-BGA RoHS:否 类别:RF/IF 和 RFID >> RF 混频器 系列:AD6635 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:100 系列:- RF 型:W-CDMA 频率:2.11GHz ~ 2.17GHz 混频器数目:1 增益:17dB 噪音数据:2.2dB 次要属性:- 电流 - 电源:11.7mA 电源电压:2.7 V ~ 3.3 V 包装:托盘 封装/外壳:12-VFQFN 裸露焊盘 供应商设备封装:12-QFN-EP（3x3） |
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