参数资料
型号: AD6634BBC
厂商: ANALOG DEVICES INC
元件分类: 无绳电话/电话
英文描述: 80 MSPS, Dual-Channel WCDMA Receive Signal Processor (RSP)
中文描述: TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA196
封装: 15 MM X 15 MM, BGA-196
文件页数: 9/52页
文件大小: 925K
代理商: AD6634BBC
REV. 0
AD6634
–9–
MICROPROCESSOR PORT TIMING CHARACTERISTICS
1, 2
Test
Level
AD6634BBC
Typ
Parameter (Conditions)
Temp
Min
Max
Unit
MICROPROCESSOR PORT, MODE INM (MODE = 0)
MODE INM WRITE TIMING
t
SC
Control
3
to
CLK Setup Time
t
HC
Control
3
to
CLK Hold Time
t
HWR
WR
(RW) to RDY(
DTACK
) Hold Time
t
SAM
Address/Data to
WR
(RW) Setup Time
t
HAM
Address/Data to RDY(
DTACK
) Hold Time
t
DRDY
WR
(RW) to RDY(
DTACK
) Delay
t
ACC
WR
(RW) to RDY(
DTACK
) High Delay
MODE INM READ TIMING
t
SC
Control
3
to
CLK Setup Time
t
HC
Control
3
to
CLK Hold Time
t
SAM
Address to
RD
(
DS
) Setup Time
t
HAM
Address to Data Hold Time
t
DRDY
RD
(
DS
) to RDY(
DTACK
) Delay
t
ACC
RD
(
DS
) to RDY(
DTACK
) High Delay
MICROPROCESSOR PORT, MODE MNM (MODE = 1)
MODE MNM WRITE TIMING
t
SC
Control
3
to
CLK Setup Time
t
HC
Control
3
to
CLK Hold Time
t
HDS
DS
(
RD
) to
DTACK
(RDY) Hold Time
t
HRW
RW(
WR
) to
DTACK
(RDY) Hold Time
t
SAM
Address/Data to RW(
WR
) Setup Time
t
HAM
Address/Data to RW(
WR
) Hold Time
t
DDTACK
DS
(
RD
) to
DTACK
(RDY) Delay
t
ACC
RW(
WR
) to
DTACK
(RDY) Low Delay
MODE MNM READ TIMING
t
SC
Control
3
to
CLK Setup Time
t
HC
Control
3
to
CLK Hold Time
t
HDS
DS
(
RD
) to
DTACK
(RDY) Hold Time
t
SAM
Address to
DS
(
RD
) Setup Time
t
HAM
Address to Data Hold Time
t
DDTACK
DS
(
RD
) to
DTACK
(RDY) Delay
t
ACC
DS
(
RD
) to
DTACK
(RDY) Low Delay
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
2.0
2.5
7.0
3.0
5.0
8.0
4
×
t
CLK
ns
ns
ns
ns
ns
ns
ns
5
×
t
CLK
9
×
t
CLK
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
5.0
2.0
0.0
5.0
8.0
8
×
t
CLK
ns
ns
ns
ns
ns
ns
10
×
t
CLK
13
×
t
CLK
Full
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
IV
2.0
2.5
8.0
7.0
3.0
5.0
8.0
4
×
t
CLK
ns
ns
ns
ns
ns
ns
ns
ns
5
×
t
CLK
9
×
t
CLK
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
5.0
2.0
8.0
0.0
5.0
8.0
8
×
t
CLK
ns
ns
ns
ns
ns
ns
ns
10
×
t
CLK
13
×
t
CLK
NOTES
1
All Timing Specifications valid over VDD range of 2.25 V to 2.75 V and VDDIO range of 3.0 V to 3.6 V.
2
C
= 40 pF on all outputs, unless otherwise specified.
3
Specification pertains to control signals: R/W, (
WR
),
DS
(
RD
),
CS
.
Specifications subject to change without notice.
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