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参数资料
| 型号： | AD6634BBC |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 无绳电话/电话 |
| 英文描述： | 80 MSPS, Dual-Channel WCDMA Receive Signal Processor (RSP) |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA196 |
| 封装： | 15 MM X 15 MM, BGA-196 |
| 文件页数： | 8/52页 |
| 文件大小： | 925K |
| 代理商： | AD6634BBC |
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REV. 0
–8–
AD6634
GENERAL TIMING CHARACTERISTICS
1, 2
Test
Level
AD6634BBC
Typ
Parameter (Conditions)
Temp
Min
Max
Unit
CLK TIMING REQUIREMENTS
t
CLK
CLK Period
t
CLKL
CLK Width Low
t
CLKH
CLK Width High
RESET
TIMING REQUIREMENTS
t
RESL
RESET
Width Low
INPUT WIDEBAND DATA TIMING REQUIREMENTS
t
SI
Input to
↑
CLK Setup Time
t
HI
Input to
↑
CLK Hold Time
LEVEL INDICATOR OUTPUT SWITCHING CHARACTERISTICS
t
DLI
↑
CLK to LI (A–A, B; B–A, B) Output Delay Time
SYNC TIMING REQUIREMENTS
t
SS
SYNC (A, B, C, D) to
↑
CLK Setup Time
t
HS
SYNC (A, B, C, D) to
↑
CLK Hold Time
SERIAL PORT CONTROL TIMING REQUIREMENTS
SWITCHING CHARACTERISTICS
2
t
SCLK
SCLK Period
t
SCLKL
SCLK Low Time
t
SCLKH
SCLK High Time
INPUT CHARACTERISTICS
t
SSI
SDI to
↓
SCLK Setup Time
t
HSI
SDI to
↓
SCLK Hold Time
PARALLEL PORT TIMING REQUIREMENTS (MASTER MODE)
SWITCHING CHARACTERISTICS
3
t
DPOCLKL
↓
CLK to
↑
PCLK Delay (Divide by 1)
t
DPOCLKLL
↓
CLK to
↑
PCLK Delay (Divide by 2, 4, or 8)
t
DPREQ
↑
CLK to
↑
PxREQ Delay
t
DPP
↑
CLK to Px[15:0] Delay
INPUT CHARACTERISTICS
t
SPA
PxACK to
↓
PCLK Setup Time
t
HPA
PxACK to
↓
PCLK Hold Time
PARALLEL PORT TIMING REQUIREMENTS (SLAVE MODE)
SWITCHING CHARACTERISTICS
3
t
POCLK
PCLK Period
t
POCLKL
PCLK Low Period (when PCLK Divisor = 1)
t
POCLKH
PCLK High Period (when PCLK Divisor = 1)
t
DPREQ
↑
CLK to
↑
PxREQ Delay
t
DPP
↑
CLK to Px[15:0] Delay
INPUT CHARACTERISTICS
t
SPA
PxACK to
↓
PCLK Setup Time
t
HPA
PxACK to
↓
PCLK Hold Time
LINK PORT TIMING REQUIREMENTS
SWITCHING CHARACTERISTICS
3
t
RDLCLK
↑
PCLK to
↑
LxCLKOUT Delay
t
FDLCLK
↓
PCLK to
↓
LxCLKOUT Delay
t
RLCLKDAT
↑
LCLKOUT to Lx[7:0] Delay
t
FLCLKDAT
↓
LCLKOUT to Lx[7:0] Delay
Full
Full
Full
I
IV
IV
12.5
5.6
5.6
ns
ns
ns
0.5
×
t
CLK
0.5
×
t
CLK
Full
I
30.0
ns
Full
Full
IV
IV
2.0
1.0
ns
ns
Full
IV
3.3
10.0
ns
Full
Full
IV
IV
2.0
1.0
ns
ns
Full
Full
Full
IV
IV
IV
16
3.0
3.0
ns
ns
ns
Full
Full
IV
IV
1.0
1.0
ns
ns
Full
Full
IV
IV
6.5
8.3
10.5
14.6
1.0
0.0
ns
ns
ns
ns
+7.0
–3.0
ns
ns
Full
Full
Full
I
IV
IV
12.5
2.0
2.0
ns
ns
ns
ns
ns
0.5
×
t
POCLK
0.5
×
t
POCLK
10.0
11.0
1.0
1.0
ns
ns
Full
Full
Full
Full
IV
IV
IV
IV
2.5
0
2.9
2.2
ns
ns
ns
ns
0
0
NOTES
1
All Timing Specifications valid over VDD range of 2.25 V to 2.75 V and VDDIO range of 3.0 V to 3.6 V.
2
C
LOAD
= 40 pF on all outputs unless otherwise specified
3
The timing parameters for Px[15:0], PxREQ, PxACK, LxCLKOUT, Lx[7:0] apply for port A and B (x stands for A or B).
Specifications subject to change without notice.
相关PDF资料 |
PDF描述 |
|---|---|
| AD6634PCB | 80 MSPS, Dual-Channel WCDMA Receive Signal Processor (RSP) |
| AD6635 | 4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP) |
| AD6635BB | 4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP) |
| AD6636 | 150 MSPS Wideband Digital Down-Converter (DDC) |
| AD6636BBCZ1 | 150 MSPS Wideband Digital Down-Converter (DDC) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD6634BBCZ | 功能描述:IC RSP 80MSPS DUAL 196CSPBGA RoHS:是 类别:RF/IF 和 RFID >> RF 混频器 系列:AD6634 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:100 系列:- RF 型:W-CDMA 频率:2.11GHz ~ 2.17GHz 混频器数目:1 增益:17dB 噪音数据:2.2dB 次要属性:- 电流 - 电源:11.7mA 电源电压:2.7 V ~ 3.3 V 包装:托盘 封装/外壳:12-VFQFN 裸露焊盘 供应商设备封装:12-QFN-EP（3x3） |
| AD6634BC/PCB | 制造商:Analog Devices 功能描述:WCDMA RECEIVE SGNL PROCESSOR - Bulk |
| AD6634PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:80 MSPS, Dual-Channel WCDMA Receive Signal Processor (RSP) |
| AD6635 | 制造商:AD 制造商全称:Analog Devices 功能描述:4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP) |
| AD6635BB | 功能描述:IC RSP 80MSPS QUAD 324-BGA RoHS:否 类别:RF/IF 和 RFID >> RF 混频器 系列:AD6635 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:100 系列:- RF 型:W-CDMA 频率:2.11GHz ~ 2.17GHz 混频器数目:1 增益:17dB 噪音数据:2.2dB 次要属性:- 电流 - 电源:11.7mA 电源电压:2.7 V ~ 3.3 V 包装:托盘 封装/外壳:12-VFQFN 裸露焊盘 供应商设备封装:12-QFN-EP（3x3） |
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