参数资料
| 型号： | AD9735BBCZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 40/72页 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT 1.2GSPS 160-CSPBGA |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 1 |
| 位数： | 12 |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 电压电源： | 模拟和数字 |
| 功率耗散（最大）： | 550mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 160-LFBGA，CSPBGA |
| 供应商设备封装： | 160-CSPBGA（12x12） |
| 包装： | 托盘 |
| 输出数目和类型： | 2 电流，单极 |
| 采样率（每秒）： | 1.2G |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页当前第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页
AD9734/AD9735/AD9736
Rev. A | Page 45 of 72
AD973x BIST PROCEDURE
1.
Set RESET pin = 1.
2.
Set input DATA = 0x0000 for signed (0x2000 for
unsigned).
3.
Enable DATACLK_IN if it is not already running.
4.
Run for at least 16 DATACLK_IN cycles.
5.
Set RESET pin = 0.
6.
Run for at least 16 DATACLK_IN cycles.
7.
Set RESET pin = 1.
8.
Run for at least 16 DATACLK_IN cycles.
9.
Set RESET pin = 0.
10.
Set desired operating mode (1× mode and signed data are
default values and expected for the supplied BIST vectors).
11.
Set CLEAR (Reg. 17, Bit 0), SYNC_EN (Reg. 17, Bit 1),
and LVDS_EN (Reg. 17, Bit 2) high.
12.
Wait 50 DATACLK_IN cycles to allow 0s to propagate
through and clear sync signatures.
13.
Set CLEAR low.
14.
Read all signature registers (Reg. 21, Reg. 20, Reg. 19, and
Reg. 18) for each of the four SEL (Reg. 17, Bits 7:6) values
and verify they are all 0x00.
LVDS Phase 1
a.
Reg. 17 set to 0x26 (SEL1 = 0, SEL0 = 0,
SIG_READ = 1, LVDS_EN = 1, SYNC_EN = 1).
b.
Read Reg. 20, Reg. 19, Reg. 18, and Reg. 17.
LVDS Phase 2
a.
Reg. 17 set to 0x66 (SEL1= 0, SEL0 = 1,
SIG_READ = 1, LVDS_EN = 1, SYNC_EN = 1).
b.
Read Reg. 20, Reg. 19, Reg. 18, and Reg. 17.
SYNC Phase 1
a.
Reg. 17 set to 0xA6 (SEL1= 1, SEL0 = 0,
SIG_READ = 1, LVDS_EN = 1, SYNC_EN = 1).
b.
Read Reg. 20, Reg. 19, Reg. 18, and Reg. 17.
SYNC Phase 2
a.
Reg. 17 set to 0xE6 (SEL1= 1, SEL0 = 1,
SIG_READ = 1, LVDS_EN = 1, SYNC_EN = 1).
b.
Read Reg. 20, Reg. 19, Reg. 18, and Reg. 17.
15.
Clock the BIST vector into the AD973x.
16.
After the BIST vector is clocked into the part, hold DATA
= 0x0000 for signed (0x2000 for unsigned); otherwise, the
additional nonzero data changes the signature.
17.
Read all signature registers (Reg. 21, Reg. 20, Reg. 19, and
Reg. 18, as described in Step 14 ) for each of the four SEL
(Reg. 17, Bits 7:6) values, and verify that they match the
expected signatures shown in Table 25.
18.
Flush the BIST circuitry. This must be done once before
valid data can be read. Loop back to Step 11 and rerun the
test to obtain the correct result.
Each time BIST mode is entered, this flush needs to
be performed once. Multiple BIST runs can be performed
without reflushing, as long as the device remains in
BIST mode.
AD973x EXPECTED BIST SIGNATURES
The BIST vectors provided on the AD973x-EB CD are in signed
mode, so no programming is necessary for the part to pass the
BIST. The BIST vector is for 1×, no FIFO, and signed data.
For testing all 14 input bits, use the vector all_bits_unsnew.txt
and verify against the signatures in Table 25.
Table 25. Expected BIST Data Readback for All Bits
LVDS Phase 1
LVDS Phase 2
SYNC Phase 1
SYNC Phase 2
CF71487C
66DF5250
CF71487C
66DF5250
For individual bit tests, use the vectors named bitn.txt (where n
is the desired bit number being tested) and compare them
against the values in Table 26.
Table 26. Expected BIST Data Readback for Individual Bits
Vector
Bit
Number
LVDS Rise
Expected
LVDS Fall
Expected
bit0.txt
0
AABF0A00
2A400500
bit1.txt
1
2BBF0A00
6B400500
bit2.txt
2
29BE0A00
E9400500
bit3.txt
3
2DBC0A00
ED410500
bit4.txt
4
25B80A00
E5430500
bit5.txt
5
35B00A00
F5470500
bit6.txt
6
15A00A00
D54F0500
bit7.txt
7
55800A00
955F0500
bit8.txt
8
D5C00A00
157F0500
bit9.txt
9
D5410A00
153E0500
bit10.txt
10
D5430B00
15BC0500
bit11.txt
11
D5470900
15B80400
bit12.txt
12
D54F0D00
15B00600
bit13.txt
13
D55F0500
15A00200
Note the following for Table 26:
The term rise refers to Phase 1 and fall refers to Phase 2.
Byte order is Decimal Register Address 21, Address 20,
Address 19, and Address 18.
SYNC phase should always equal LVDS phase in 1× mode.
相关PDF资料 |
PDF描述 |
|---|---|
| AD7225LPZ | IC DAC 8BIT QUAD W/AMP 28-PLCC |
| AD9776BSVZ | IC DAC 12BIT DUAL 1GSPS 100TQFP |
| ADDAC80D-CBI-V | IC DAC 12BIT LOW COST 24-CDIP |
| AD7247KNZ | IC DAC 12BIT W/AMP W/BUFF 24-DIP |
| VI-2NW-IV-F1 | CONVERTER MOD DC/DC 5.5V 150W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9735BBCZ1 | 制造商:AD 制造商全称:Analog Devices 功能描述:10-/12-/14-Bit, 1200 MSPS DACS |
| AD9735BBCZRL | 功能描述:IC DAC 12BIT 1.2GSPS 160-CSPBGA RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Data Converter Fundamentals DAC Architectures 标准包装:750 系列:- 设置时间:7µs 位数:16 数据接口:并联 转换器数目:1 电压电源:双 ± 功率耗散（最大）:100mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-LCC（J 形引线） 供应商设备封装:28-PLCC（11.51x11.51） 包装:带卷 (TR) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:143k |
| AD9735BBCZRL1 | 制造商:AD 制造商全称:Analog Devices 功能描述:10-/12-/14-Bit, 1200 MSPS DACS |
| AD9735-DPG2-EBZ | 功能描述:BOARD EVAL FOR AD9735 RoHS:是 类别:编程器，开发系统 >> 评估板 - 数模转换器 (DAC) 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- DAC 的数量:4 位数:12 采样率（每秒）:- 数据接口:串行，SPI? 设置时间:3µs DAC 型:电流/电压 工作温度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9735-EB | 制造商:Analog Devices 功能描述: |
发布紧急采购，3分钟左右您将得到回复。